SYSTEM VERILOG IDENT ERROR

[terabits]

module test;

reg a,b;

initial
begin
a =0;
b = 0;
#10 a= 1;
#10;
$finish;

end

always @ (a or b)
begin
assert (a == b) $display (" a eual to b") ;
else $display (" a is not eual to b") ;
end

endmodule

Model Technology ModelSim SE vlog 6.0b Compiler 2004.12 Dec 1 2004
-- Compiling module test
** Error: assert.sv(17): near "assert": expecting: IDENT THIS

It gives me this error, could any one let me know what causes this ??

 

[terabits]

well i found the answer myself...it is the version problem previously i
was using 6.0, now changed to 6.1..problem solved.
but modelsim could give some meaningful message rather than IDENT..and
stuff like that.
On Dec 12, 1:07 pm, "terabits" <tera.b...@gmail.com> wrote:

module test;

reg a,b;

initial
begin
a =0;
b = 0;
#10 a= 1;
#10;
$finish;

end

always @ (a or b)
begin
assert (a == b) $display (" a eual to b") ;
else $display (" a is not eual to b") ;
end

endmodule

Model Technology ModelSim SE vlog 6.0b Compiler 2004.12 Dec 1 2004
-- Compiling module test
** Error: assert.sv(17): near "assert": expecting: IDENT THIS

It gives me this error, could any one let me know what causes this ??