System verilog assistance

M

meenz

Guest
Hi all,
I am new to system verilog and i need to develop a TB in system
verilog for I2C core.
Could anyone please guide me on how to organise my SV test bench
( organisation of classes etc).

Also if anybody has a complete system verilog TB for any application
could you share it with me

Regards
Meenz
 
Hi,
I think that constrained random verification can be used to test I2C. It
works very well for communication application.
Most of CRV testbenches are very similar and you can find description of
basic architecture on http://www.pulselogic.com.pl/en/index.html (New
Technologies Section)
but it depends want kind of tool you have for simulation. Most vendors
provide library of basic classes
for verification like random generators, scoreboards, comparators and others
for displaying messages etc.
For example, Mentor provides AVM library, Synopsys VMM. You should use a
library provided by your vendor
and follow CRV techniques recommended by your vendor. Each library has a
verification manual or similar document.

Best Regards,
Steve



"meenz" <meenz.tronix@gmail.com> wrote in message
news:1185970598.027105.45810@j4g2000prf.googlegroups.com...
Hi all,
I am new to system verilog and i need to develop a TB in system
verilog for I2C core.
Could anyone please guide me on how to organise my SV test bench
( organisation of classes etc).

Also if anybody has a complete system verilog TB for any application
could you share it with me

Regards
Meenz
Click to expand...
 
Hi Meenz,

My site trusster.com has a verification framework in SystemVerilog
that is open source. It runs on MTI and Synopsys simulators. There is
also an example based on uart, which should be close to i2C.

Take Care,
Mike

"meenz" <meenz.tro...@gmail.com> wrote in message

news:1185970598.027105.45810@j4g2000prf.googlegroups.com...

Hi all,
I am new to system verilog and i need to develop a TB in system
verilog for I2C core.
Could anyone please guide me on how to organise my SV test bench
( organisation of classes etc).

Also if anybody has a complete system verilog TB for any application
could you share it with me

Regards
Meenz
Click to expand...
 
Hi Mike and Steve,
Thanks for replying to my post.
The I2c device that I am using is a master only. So so far i have
crated an interface ( one for the driver end and the other for the
slave end)
My I2C core interacts with a wishbone I/F . NOw i am not able to
decide how i should organise my driver . The inputs data and address
have to applied in a sequence and there is a continuous handshake. so
how do i create a class and what should i randomize and at the same
time make sure that the correct protocol is followed( the appropriate
registers are stored with appropriate values, slave address is sent
before data etc..)

could one of you maybe write just a couple of lines of code ato
explain this to me

Thanks and regards
Meenz

On Aug 3, 8:58 pm, "mmi...@gmail.com" <mmi...@gmail.com> wrote:
Hi Meenz,

My site trusster.com has a verification framework in SystemVerilog
that is open source. It runs on MTI and Synopsys simulators. There is
also an example based on uart, which should be close to i2C.

Take Care,
Mike

"meenz" <meenz.tro...@gmail.com> wrote in message

news:1185970598.027105.45810@j4g2000prf.googlegroups.com...

Hi all,
I am new to system verilog and i need to develop a TB in system
verilog for I2C core.
Could anyone please guide me on how to organise my SV test bench
( organisation of classes etc).

Also if anybody has a complete system verilog TB for any application
could you share it with me

Regards
Meenz
Click to expand...
 
Hi Meenz,

Lots of good questions. To start with, consider making a configuration
class to hold values like normal/extended addressing, base frequency,
etc. An instance can then be randomized for different configurations.

Now, there are two drivers to consider. One talks to your RTL and is
concerned with writing registers. The other sits on the wires and
follows/checks the protocol. There are different classes. Also, I call
the wire using class a bus functional model, or BFMs because it is bi-
directional (the protocol is that way). Finally, I call the one that
interacts at the register level of your RTL a software functional
model, because it is the software interface.

As for the data part, consider making that a class as well. The basic
I2C unit is a start address and an array of data. You probably also
want a status word to indicate whether to inject or report errors.

Putting this together... (code just typed in and may not compile)

package i2c;

class configuration;
rand int frequency;
rand bit extended_addressing;
//add constraints here
endclass

interface wires; //make a "real interface" in your top level code and
pass it to the new of the bfm class.
wire scl;
wire sca;
endinterface

class bfm;
function new (string name, configuration c, virtual wires w);
endclass

class sfm;
function new (string name, configuration c, int
start_register_address);
endclass

endpackage

There is much to implement and we haven't even began talking about the
checking side.

Interesting, my UART examples also use the wishbone interface, so
there should be code there to use. Also the uart follows the naming
above.

I do hope you will take a look at the examples I have as they address
your great questions!

Hope this helps,
Mike

On Aug 7, 1:59 am, meenz <meenz.tro...@gmail.com> wrote:
Hi Mike and Steve,
Thanks for replying to my post.
The I2c device that I am using is a master only. So so far i have
crated an interface ( one for the driver end and the other for the
slave end)
My I2C core interacts with a wishbone I/F . NOw i am not able to
decide how i should organise my driver . The inputs data and address
have to applied in a sequence and there is a continuous handshake. so
how do i create a class and what should i randomize and at the same
time make sure that the correct protocol is followed( the appropriate
registers are stored with appropriate values, slave address is sent
before data etc..)

could one of you maybe write just a couple of lines of code ato
explain this to me

Thanks and regards
Meenz

On Aug 3, 8:58 pm, "mmi...@gmail.com" <mmi...@gmail.com> wrote:

Hi Meenz,

My site trusster.com has a verification framework in SystemVerilog
that is open source. It runs on MTI and Synopsys simulators. There is
also an example based on uart, which should be close to i2C.

Take Care,
Mike

"meenz" <meenz.tro...@gmail.com> wrote in message

news:1185970598.027105.45810@j4g2000prf.googlegroups.com...

Hi all,
I am new to system verilog and i need to develop a TB in system
verilog for I2C core.
Could anyone please guide me on how to organise my SV test bench
( organisation of classes etc).

Also if anybody has a complete system verilog TB for any application
could you share it with me

Regards
Meenz
Click to expand...
 
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