System On Chip From Microsemi

[rickman]

I guess I stopped looking at the Microsemi products some time back. The
SOC devices put out by Actel were ok, but the price was up there even
for the smallest one, around $50. I was looking on Digikey and it seems
their prices have come down and the new Smart Fusion 2 devices are even
lower. The cheapest part is $16 qty at Digikey.

These SOCs don't have any analog unless you consider the crystal clock
to be analog, lol. Still, they have all the digital stuff you might
want and are a lot cheaper than the Xilinx and Altera SOC lines.

BTW, I found that Mouser doesn't seem to carry Xilinx anymore. When I
search on Xilinx on the Mouser site they bring up the Altera page, lol.

--

Rick

 

I agree, the SmartFusion2 devices are actually very competitive and they have some strengths that are absent from their competition. They are flash-based, which has some distinct benefits:
* No external configuration device is required.
* The device is instant-on, i.e. you do not have this long dead configuration period.
* The flash gate architecture provides inherent single-event-upset (SEU) immunity. For long term reliability, SRAM-based FPGA's are vulnerable to error events when struck by cosmic rays. This is a strength, especially in aeronautics/space.
* When all the clocks are stopped, the flash architecture consumes very little standby current. In general, these devices are super low power.

For an SoC, the SmartFusion2 security features are really superior. Secure key storage with active mesh protection and tamper detection, embedded AES256/SHA256, the physically uncloneable function (PUF) and the true random number generator of the S devices are ideal for secure machine-to-machine communication and for protecting IP.
Also, they have certified anti-key-hacking mechanisms like differential power analysis (DPA) resistance. Read up on how FPGA keys can be compromised with DPA:
http://www.microsemi.com/document-portal/doc_download/131563-protecting-fpgas-from-power-analysis

In terms of development, Avnet recently started selling a super low-cost development board, the SmartFusion2 KickStart kit, that has a 10k gate SoC with a 166MHz Cortex M3 - the M2S010S. It is only $59.95 and is a little USB-powered module in the Arduino form factor with some sensors and PMODs for expansion. Their reference design examples make it pretty quick to get up and running.
http://www.em.avnet.com/en-us/design/drc/Pages/Microsemi-SmartFusion2-KickStart-Development-Kit.aspx

SR

 

[Meshenger]

I agree, the SmartFusion2 devices are actually very competitive and they have some strengths that are absent from their competition. They are flash-based, which has some distinct benefits:
* No external configuration device is required.
* The device is instant-on, i.e. you do not have this long dead configuration period.
* The flash gate architecture provides inherent single-event-upset (SEU) immunity. For long term reliability, SRAM-based FPGA's are vulnerable to error events when struck by cosmic rays. This is a strength, especially in aeronautics/space.
* When all the clocks are stopped, the flash architecture consumes very little standby current. In general, these devices are super low power.

For an SoC, the SmartFusion2 security features are really superior. Secure key storage with active mesh protection and tamper detection, embedded AES256/SHA256, the physically uncloneable function (PUF) and the true random number generator of the S devices are ideal for secure machine-to-machine communication and for protecting IP.
Also, they have certified anti-key-hacking mechanisms like differential power analysis (DPA) resistance. Read up on how FPGA keys can be compromised with DPA:
http://www.microsemi.com/document-portal/doc_download/131563-protecting-fpgas-from-power-analysis

In terms of development, Avnet recently started selling a super low-cost development board, the SmartFusion2 KickStart kit, that has a 10k gate SoC with a 166MHz Cortex M3 - the M2S010S. It is only $59.95 and is a little USB-powered module in the Arduino form factor with some sensors and PMODs for expansion. There is a Bluetooth LE module on the board and some Android & Windows demo's. Their reference design examples make it pretty quick to get up and running.
http://www.em.avnet.com/en-us/design/drc/Pages/Microsemi-SmartFusion2-KickStart-Development-Kit.aspx

SR

 

[rickman]

On 10/3/2015 9:39 PM, zoomboom718@gmail.com wrote:

I agree, the SmartFusion2 devices are actually very competitive and they have some strengths that are absent from their competition. They are flash-based, which has some distinct benefits:
* No external configuration device is required.
* The device is instant-on, i.e. you do not have this long dead configuration period.
* The flash gate architecture provides inherent single-event-upset (SEU) immunity. For long term reliability, SRAM-based FPGA's are vulnerable to error events when struck by cosmic rays. This is a strength, especially in aeronautics/space.

Not trying to be retarded, as I have not checked the data sheet on this,
but isn't the FPGA fabric SRAM based and loaded (albeit more quickly
than a serial config) from the internal Flash? I'm more familiar with
Lattice Flash parts and that's what they do. Instead of large fractions
of a second the config time is a couple of ms. The SRAM allows you to
change the config from JTAG without flashing the part. Don't the
MicroSemi parts do that too?

I know Actel (now MicroSemi) is *very* familiar with the aerospace
market. I expect that is a large part of their sales.


> * When all the clocks are stopped, the flash architecture consumes very little standby current. In general, these devices are super low power.

I *did* glance at the data sheet about this. They are better than parts
from the big two, but Lattice has parts that are much better than the
numbers I saw. Still, this is an SoC and Lattice isn't there yet.

For an SoC, the SmartFusion2 security features are really superior. Secure key storage with active mesh protection and tamper detection, embedded AES256/SHA256, the physically uncloneable function (PUF) and the true random number generator of the S devices are ideal for secure machine-to-machine communication and for protecting IP.
Also, they have certified anti-key-hacking mechanisms like differential power analysis (DPA) resistance. Read up on how FPGA keys can be compromised with DPA:
http://www.microsemi.com/document-portal/doc_download/131563-protecting-fpgas-from-power-analysis

I won't say I understand it, but I have seen somethings about this. But
"true random number generator"??? My understanding is this is virtually
impossible. I haven't read about this. Is it based on noise from a
diode or something? I recall a researcher trying that and it was good,
but he could never find the source of a long term DC bias.

In terms of development, Avnet recently started selling a super low-cost development board, the SmartFusion2 KickStart kit, that has a 10k gate SoC with a 166MHz Cortex M3 - the M2S010S. It is only $59.95 and is a little USB-powered module in the Arduino form factor with some sensors and PMODs for expansion. Their reference design examples make it pretty quick to get up and running.
http://www.em.avnet.com/en-us/design/drc/Pages/Microsemi-SmartFusion2-KickStart-Development-Kit.aspx

I saw that and thought, DARN IT! Often the manufacturer produces rather
expensive eval boards (which MicroSemi did in this case) but Avnet spun
a low cost one. I was hoping to find a market for a new product. But
the low cost board is lacking a lot of I/O features like Ethernet.
Maybe there is some potential for an add on board to bring it up to eval
board functionality. They have a development board that looks like it
has every bell and whistle in the book! I don't think I *want* to
duplicate that.

I wish I had an app for this device. I also wish it were a bit cheaper
still.

BTW, they have training on the KickStart kit including a kit for $100.
I'm not sure why they are asking for the $40 above the cost of the kit.
That isn't even paying the trainer to show up!

I'm having a little trouble finding much info on board routing the VF256
package. It seems to not be included in most of their info. I guess it
would be the same as the VF400 package? Seems every chip maker has a
different name for the same package.

--

Rick

 

[Thomas Stanka]

Am Sonntag, 4. Oktober 2015 04:23:38 UTC+2 schrieb rickman:

Not trying to be retarded, as I have not checked the data sheet on this,
but isn't the FPGA fabric SRAM based and loaded (albeit more quickly
than a serial config) from the internal Flash?

The functional configuration of each cell is controlled by distributed flash. Else they would not be able to reach their SEE immunity for configuration, and would have trouble reaching their bootup times (aka instant-on).

regards,

Thomas

 

[Kevin Neilson]

I won't say I understand it, but I have seen somethings about this. But
"true random number generator"??? My understanding is this is virtually
impossible. I haven't read about this. Is it based on noise from a
diode or something? I recall a researcher trying that and it was good,
but he could never find the source of a long term DC bias.

I don't know how these guys do it, but you can make a decent true random number generator with ring oscillators. I read one paper that described using several of these along with non-linear feedback shift registers to get a good random number.

 

[Meshenger]

About SEU, I think the way this works is that yes as with any SRAM device the data or settings can be disrupted by an SEU and there is nothing one can do about that. The device could possibly recover from that though. But if the configuration, i.e. the logic and connection grid, gets disrupted, the chances of irreversible damage is much greater and less likely to be temporary. The flash-based gate structure protects logic configuration against that.

The SF2 random number generator is clever and seeded by, amongst other sources, RAM power-up conditions, shown to be "random enough". How random is random enough for cryptography? This is a good article with some good comments in it:
http://www.eetimes.com/author.asp?section_id=36&doc_id=1326572
So "SP800-90 cryptographic-grade Non-Deterministic Random Bit Generator" might be more correct than "true RNG". So it follows recommendations in a NIST special publication on seeding, checking and maintaining random bits. You would probably have to invent something new to improve on that.

In terms of Ethernet on the KickStart eval/development board, one can add an Arduino shield for that. There is Bluetooth on-board but not Ethernet.

SR

 

[rickman]

On 10/5/2015 7:06 AM, Thomas Stanka wrote:

Am Sonntag, 4. Oktober 2015 04:23:38 UTC+2 schrieb rickman:
Not trying to be retarded, as I have not checked the data sheet on
this, but isn't the FPGA fabric SRAM based and loaded (albeit more
quickly than a serial config) from the internal Flash?

The functional configuration of each cell is controlled by
distributed flash. Else they would not be able to reach their SEE
immunity for configuration, and would have trouble reaching their
bootup times (aka instant-on).

I guess I am just hardwired to think of the config memory as RAM. But I
don't see how they make the rest of the chip immune to SEE. The logic
units have a FF which must be immune which I don't see described. I
also don't see mention of the fabric memory being SEE immune. I guess
they bury that in some radiation related document somewhere. I do see
where the refer to certain part of the chip as only "SEU Resistant".

--

Rick

 

[Jon Elson]

rickman wrote:

BTW, I found that Mouser doesn't seem to carry Xilinx anymore. When I
search on Xilinx on the Mouser site they bring up the Altera page, lol.

Xilinx is only carried through Digi-Key and Avnet, for the last few years.

Jon

 

[rickman]

On 10/5/2015 1:37 PM, Meshenger wrote:

In terms of Ethernet on the KickStart eval/development board, one can
add an Arduino shield for that. There is Bluetooth on-board but not
Ethernet.

The only Arduino shields I have seen are general purpose interfaces
which duplicate the MAC internal to the SF2. This means it would not be
code compatible with the SF2 Ethernet and so not much value using the
Kickstart board for software development of a SF2 project. I think the
SF2 only needs a Phy and the transformer.

I would consider designing an add-on board to use the internal Ethernet
MAC and make the I/O capability compatible with the Microsemi eval
board. I might add a few bells and whistles too.

--

Rick

 

[rickman]

On 10/5/2015 1:12 PM, Kevin Neilson wrote:

I won't say I understand it, but I have seen somethings about this. But
"true random number generator"??? My understanding is this is virtually
impossible. I haven't read about this. Is it based on noise from a
diode or something? I recall a researcher trying that and it was good,
but he could never find the source of a long term DC bias.


I don't know how these guys do it, but you can make a decent true random number generator with ring oscillators. I read one paper that described using several of these along with non-linear feedback shift registers to get a good random number.

Again, I don't know for sure, but I think ring oscillators make very
*poor* random number generators because they are easily linked to noise
sources such as clocks on the chip.

--

Rick

 

[Theo Markettos]

rickman <gnuarm@gmail.com> wrote:

Again, I don't know for sure, but I think ring oscillators make very
*poor* random number generators because they are easily linked to noise
sources such as clocks on the chip.

Yes:
http://www.cl.cam.ac.uk/~atm26/papers/markettos-ches2009-inject-trng.pdf

That has been confirmed to me by various industrial security folks.

Theo