system calls

[agape]

I have compiled all my codes in System Verilog 3.1 with Modelsim 6.0.
Upon runnng, I get the following:
# ** Warning: (vsim-3198) [TSCALE] - Module 'packet_checker' does not
have a `timescale directive in effect, but previous modules do.
# Region: /exuunit_test/exu_frpu_checker
# ** Error: (vsim-PLI-3691)
/group/users/topunit/models/v060_user2/vhdl/exuunit_test/exuunit_test.v(567):
Expected a system task, not a system function '$sscanf'.
# Region: /exuunit_test/wb_inject

And much more lines with $fgets, $ungetc and ...

Do I know to compile PLIs or other files in 6.0 to get this to work?
Thank You.

 

[agape]

This is now resolved. I figured it out. It appears that you have to
return the result of sscanf to a variable.
Thanks
bionic_man1@yahoo.com (agape) wrote in message news:<3e5aae09.0411110749.24a6486c@posting.google.com>...

I have compiled all my codes in System Verilog 3.1 with Modelsim 6.0.
Upon runnng, I get the following:
# ** Warning: (vsim-3198) [TSCALE] - Module 'packet_checker' does not
have a `timescale directive in effect, but previous modules do.
# Region: /exuunit_test/exu_frpu_checker
# ** Error: (vsim-PLI-3691)
/group/users/topunit/models/v060_user2/vhdl/exuunit_test/exuunit_test.v(567):
Expected a system task, not a system function '$sscanf'.
# Region: /exuunit_test/wb_inject

And much more lines with $fgets, $ungetc and ...

Do I know to compile PLIs or other files in 6.0 to get this to work?
Thank You.

 

[Srinivasan Venkataramanan]

Hi,
SV LRM (3.1a) allows void'(fn_fname()) to discard return value of a
function. See LRM section 10.3.2

Srinivasan

--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned
"agape" <bionic_man1@yahoo.com> wrote in message
news:3e5aae09.0411120507.10512156@posting.google.com...

This is now resolved. I figured it out. It appears that you have to
return the result of sscanf to a variable.
Thanks
bionic_man1@yahoo.com (agape) wrote in message
news:<3e5aae09.0411110749.24a6486c@posting.google.com>...
I have compiled all my codes in System Verilog 3.1 with Modelsim 6.0.
Upon runnng, I get the following:
# ** Warning: (vsim-3198) [TSCALE] - Module 'packet_checker' does not
have a `timescale directive in effect, but previous modules do.
# Region: /exuunit_test/exu_frpu_checker
# ** Error: (vsim-PLI-3691)

/group/users/topunit/models/v060_user2/vhdl/exuunit_test/exuunit_test.v(567)

:

Expected a system task, not a system function '$sscanf'.
# Region: /exuunit_test/wb_inject

And much more lines with $fgets, $ungetc and ...

Do I know to compile PLIs or other files in 6.0 to get this to work?
Thank You.