Synthezised

[Joshdak]

I apologize, I'm not that new in digital design, so please forgive me if I
ask silly questions. But, if I have a code like:

type memory is array (0 to 7,0 to 7) of std_logic_vector(15 downto 0);
signal mymem: memory;

How will this be synthesized? Is this the ideal implementation for a fast
memory?
Does this equal what you would refer to as a "Register File"? If not, what
are the difference in utilizing a Register File and just use a 2-D array?

Best Regards

 

[Mike Treseler]

Joshdak wrote:

type memory is array (0 to 7,0 to 7) of std_logic_vector(15 downto 0);
signal mymem: memory;
How will this be synthesized?

A signal alone represents a wire, but
synthesis requires a complete entity
architecture pair.

Is this the ideal implementation for a fast memory?

It is incomplete. Start with the memory templates
provided by the device or synthesis vendor.
If you do it right for the right fpga you will get
a block RAM. Otherwise the RAM will be built out
of logic cells -- gates and flops.


-- Mike Treseler