D
Drashti Patel
Guest
hi every one,
I am working on xilinx 14.1.
I am trying to read a text file containing 16384 binary data(each of 10 bits) and store it in to RAM.
As I execute following code, and tries to synthesize it, the synthesizing process keeps running and it never stops.
console block shows the comment :
Elaborating entity <win_test> (architecture <bev> from library <work>.
Non-constant loop found; will execute up to 5000 iterations
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity win_test is
port (address : in std_logic_vector(14 downto 0);
dataout : out std_logic_vector(9 downto 0));
end entity;
architecture bev of win_test is
type mem is array (0 to 16384) of std_logic_vector(9 downto 0);
signal t_mem : mem;
begin
process(address)
FILE f : TEXT;
constant filename : string :="win_data - Copy.txt";
VARIABLE L : LINE;
variable i : integer:=0;
variable b : std_logic_vector(9 downto 0);
begin
File_Open (f,FILENAME, read_mode);
while ((i<=16384) and (not EndFile (f))) loop
readline (f, l);
next when l(1) = '#'; -- to read first line
read(l, b);
t_mem(i) <= b;
i := i + 1;
end loop;
File_Close (f);
dataout<=t_mem(conv_integer(address));
end process;
end bev;
When I tried the same code to read file containing smaller number of data(16 instead of 16384), the code synthesized successfully.
Please help me with this.
I am working on xilinx 14.1.
I am trying to read a text file containing 16384 binary data(each of 10 bits) and store it in to RAM.
As I execute following code, and tries to synthesize it, the synthesizing process keeps running and it never stops.
console block shows the comment :
Elaborating entity <win_test> (architecture <bev> from library <work>.
Non-constant loop found; will execute up to 5000 iterations
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity win_test is
port (address : in std_logic_vector(14 downto 0);
dataout : out std_logic_vector(9 downto 0));
end entity;
architecture bev of win_test is
type mem is array (0 to 16384) of std_logic_vector(9 downto 0);
signal t_mem : mem;
begin
process(address)
FILE f : TEXT;
constant filename : string :="win_data - Copy.txt";
VARIABLE L : LINE;
variable i : integer:=0;
variable b : std_logic_vector(9 downto 0);
begin
File_Open (f,FILENAME, read_mode);
while ((i<=16384) and (not EndFile (f))) loop
readline (f, l);
next when l(1) = '#'; -- to read first line
read(l, b);
t_mem(i) <= b;
i := i + 1;
end loop;
File_Close (f);
dataout<=t_mem(conv_integer(address));
end process;
end bev;
When I tried the same code to read file containing smaller number of data(16 instead of 16384), the code synthesized successfully.
Please help me with this.