Synthesizing pipelined multipliers in Synplify Pro

[Sandeep]

Does anyone have experience with synthesizing multipliers using "*"
operator in Synplify ? To pipleline the multiplier has anyone tried
the piplelining feature in Synplify and/or by attaching attributes to
output registers ? I know it works on a multiplier by itself. But in a
larger design the pipleline stages are reduced to 1 or 2 even though I
attached 4-5 registers to the multiplier output.

Sandeep

 

[Jim Lewis]

Sandeep,
Check out my paper on, "Coding a 40 x 40 Multipler".
The paper explores coding styles for coding a pipelined
multiplier.

You can find it at:
http://www.synthworks.com/papers/index.htm

Also Ray Andraka has some great papers on implementing
math in FPGAs. See: http://www.andraka.com/multipli.htm

Cheers,
Jim

Sandeep wrote:

Does anyone have experience with synthesizing multipliers using "*"
operator in Synplify ? To pipleline the multiplier has anyone tried
the piplelining feature in Synplify and/or by attaching attributes to
output registers ? I know it works on a multiplier by itself. But in a
larger design the pipleline stages are reduced to 1 or 2 even though I
attached 4-5 registers to the multiplier output.

Sandeep

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Sandeep]

Jim,
Thanks for the reference. Pretty nice. I dont want to sound like a
sales person for Synplify, but it does an incredible (better than me)
job with logic optimization and also timing driven optimization. The
problem I reported was a bug in the way I was pipelining the
multiplier. Synplify will infer if and only if the output of the
multiply is directly connected to the pipeline. I want to create a
family of multipliers from the same HDL code by inferring bit widths
without loss of performance. And I think Synplicity is pretty good at
breaking the multiply based on pipeline stages I provide. I could get
a 16x16 multiply to run at 85 MHz on a VirtexE chip. If I wanted to
run the same code at 150 MHz, I think I will switch to Virtex-II and
still let the synplify infer and map the multiply to a block
multiplier in Virtex-II or Spartans. I dont want to sound like a
software guy but for creating scalable and portable designs I like
inferring as much as possible (with minimal performance degradation).
I am interested on your thoughts on it.

Sandeep
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<1010sdfo3fmcb6d@corp.supernews.com>...

Sandeep,
Check out my paper on, "Coding a 40 x 40 Multipler".
The paper explores coding styles for coding a pipelined
multiplier.

You can find it at:
http://www.synthworks.com/papers/index.htm

Also Ray Andraka has some great papers on implementing
math in FPGAs. See: http://www.andraka.com/multipli.htm

Cheers,
Jim

Sandeep wrote:
Does anyone have experience with synthesizing multipliers using "*"
operator in Synplify ? To pipleline the multiplier has anyone tried
the piplelining feature in Synplify and/or by attaching attributes to
output registers ? I know it works on a multiplier by itself. But in a
larger design the pipleline stages are reduced to 1 or 2 even though I
attached 4-5 registers to the multiplier output.

Sandeep

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Ray Andraka]

Inference is great as long as you can live with the results. 85 MHz is trivial on a VirtexE, we
typically ran VirtexE at 160+ MHz, including multipliers bigger than 16x16, but you won't get
there very often with just inference. We get scalability by building our macros for things like
placed multipliers to automatically size to the connected bus sizes, and/or to use generics to
set up parameters. Much of my work (re)uses placed macros that are structurally instantiated
primitives. The generate statement with the ability to put loop variables in the constant
definitions (for the RLOC strings) is essential. It is one of those things that VHDL does well,
that even with the 2001 enhancements verilog still can't do.

Granted, I do give up some portability, but much of that can be recovered by changing the
library of lower level macros or even just the primitives. My xilinx libraries have, for the
most part, been updated with a "virtex" generic which causes the RLOCs to be for
virtex/virtexE/spartan2, virtexII, virtex3/spartan3,or unplaced. I have ported some of these
designs to Altera, but the bigger issue there is that the differences in chip features usually
means some high level archiectural changes in order to get a near optimal design. This is true
whether you infer or instantiate.

Sandeep wrote:

Jim,
Thanks for the reference. Pretty nice. I dont want to sound like a
sales person for Synplify, but it does an incredible (better than me)
job with logic optimization and also timing driven optimization. The
problem I reported was a bug in the way I was pipelining the
multiplier. Synplify will infer if and only if the output of the
multiply is directly connected to the pipeline. I want to create a
family of multipliers from the same HDL code by inferring bit widths
without loss of performance. And I think Synplicity is pretty good at
breaking the multiply based on pipeline stages I provide. I could get
a 16x16 multiply to run at 85 MHz on a VirtexE chip. If I wanted to
run the same code at 150 MHz, I think I will switch to Virtex-II and
still let the synplify infer and map the multiply to a block
multiplier in Virtex-II or Spartans. I dont want to sound like a
software guy but for creating scalable and portable designs I like
inferring as much as possible (with minimal performance degradation).
I am interested on your thoughts on it.

Sandeep
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<1010sdfo3fmcb6d@corp.supernews.com>...
Sandeep,
Check out my paper on, "Coding a 40 x 40 Multipler".
The paper explores coding styles for coding a pipelined
multiplier.

You can find it at:
http://www.synthworks.com/papers/index.htm

Also Ray Andraka has some great papers on implementing
math in FPGAs. See: http://www.andraka.com/multipli.htm

Cheers,
Jim

Sandeep wrote:
Does anyone have experience with synthesizing multipliers using "*"
operator in Synplify ? To pipleline the multiplier has anyone tried
the piplelining feature in Synplify and/or by attaching attributes to
output registers ? I know it works on a multiplier by itself. But in a
larger design the pipleline stages are reduced to 1 or 2 even though I
attached 4-5 registers to the multiplier output.

Sandeep

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
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