Synthesizing generate and always blocks...

[kb33]

I have a verilog file that has a generate block, followed by a couple
of always blocks. The synthesis tool is not able to synthesize......it
just goes on without giving any errors or warnings. Is it legal to
have all the three blocks in the same file?

Thanks
kb33

 

[mahesh]

On Apr 2, 9:34 am, kb33 <kanchan.devarako...@gmail.com> wrote:

I have a verilog file that has a generate block, followed by a couple
of always blocks. The synthesis tool is not able to synthesize......it
just goes on without giving any errors or warnings. Is it legal to
have all the three blocks in the same file?

Thanks
kb33

Hi KB,

It should synthesize irrespective of the # of always blks. Could
u pls pulg in that code here...for ur generate blk....Wat does it
perform....Wat synthesizer r u using..

Regards,
Mahesh