A
Andreas Schwarz
Guest
Hi,
I'm trying to synthesize a design with the fixed_pkg package in Xilinx
ISE 9.2. I'm using the version adapted for Xilinx from
http://www.eda-stds.org/fphdl/vhdl.html. Compilation works fine, but
after that I get the following, not exactly helpful error message:
=========================================================================
* Design Hierarchy Analysis
*
=========================================================================
ERROR:Xst:2683 - Unexpected error found while building hierarchy.
-->
This happens both with the synthesis test from the website above and
with my own trivial example (attached at the end of the post). You can
get the complete test project from http://www.mikrocontroller.net/attachment/25445/fixpt-test.zip.
Has anyone found a workaround to use fixed_pkg with ISE?
Thanks,
Andreas
Attachment:
architecture rtl of top is
signal x, y : sfixed (3 downto -3);
begin
x <= to_sfixed(in1, 3, -3);
y <= x * 2;
out1 <= to_slv
;
end rtl;
I'm trying to synthesize a design with the fixed_pkg package in Xilinx
ISE 9.2. I'm using the version adapted for Xilinx from
http://www.eda-stds.org/fphdl/vhdl.html. Compilation works fine, but
after that I get the following, not exactly helpful error message:
=========================================================================
* Design Hierarchy Analysis
*
=========================================================================
ERROR:Xst:2683 - Unexpected error found while building hierarchy.
-->
This happens both with the synthesis test from the website above and
with my own trivial example (attached at the end of the post). You can
get the complete test project from http://www.mikrocontroller.net/attachment/25445/fixpt-test.zip.
Has anyone found a workaround to use fixed_pkg with ISE?
Thanks,
Andreas
Attachment:
architecture rtl of top is
signal x, y : sfixed (3 downto -3);
begin
x <= to_sfixed(in1, 3, -3);
y <= x * 2;
out1 <= to_slv
;end rtl;