Synthesizeable Testbench

[Vinilkant Tejaswi]

Hi,

I recently found that it is possible to write a synthesizeable
testbench for hardware emulation using UVM methodology from a book
called Professional Verification by Paul Wilcox[Cadence systems]. Does
anybody have a example testbench for this. That would also mean that
synthesizeable testbench is similar to BIST[built in self test]..

If you have more information on this subject, I would like to learn
more.


Thanks!!
Vinil

 

[Neo]

I dont think the synthesizable TB is a new concept. its been done from
quite a long time for verification acceleration.