A
aravindcet2003@gmail.com
Guest
Hi all.... What is the exact meaning of 'synthesizable'???
K
KJ
Guest
<aravindcet2003@gmail.com> wrote in message
news:1171812965.260692.63090@q2g2000cwa.googlegroups.com...
http://dictionary.reference.com/browse/synthesize
Within the context of the VHDL language (and any other hardware description
language) 'synthesizable' is generally taken to mean something like "can be
transformed into a physical part". Whether a particular VHDL statement is
'synthesizable' or not depends on the technology planned to realize the
final 'physical part'. A simple example is
b <= a after 10 ns;
This simple statement is not generally synthesizable in most FPGA/CPLD
currently around, but in fact can be realized with a simple delay line which
is rather oldish (but still useful) technology.
Kevin Jennings
news:1171812965.260692.63090@q2g2000cwa.googlegroups.com...
When looking for definitions, try the dictionary....
http://dictionary.reference.com/browse/synthesize
Within the context of the VHDL language (and any other hardware description
language) 'synthesizable' is generally taken to mean something like "can be
transformed into a physical part". Whether a particular VHDL statement is
'synthesizable' or not depends on the technology planned to realize the
final 'physical part'. A simple example is
b <= a after 10 ns;
This simple statement is not generally synthesizable in most FPGA/CPLD
currently around, but in fact can be realized with a simple delay line which
is rather oldish (but still useful) technology.
Kevin Jennings
N
Neo
Guest
Hi,
Systhesizable refers to the capability of the sysnthesis tools to
implement the given program in hardware. So in that sense all delays
come under non-sysnthesiszable as the tools havent yet advanced to a
stage where they can guarantee specific delays. May be they will
become feasible a few years down the line.
cheers,
Neo
Systhesizable refers to the capability of the sysnthesis tools to
implement the given program in hardware. So in that sense all delays
come under non-sysnthesiszable as the tools havent yet advanced to a
stage where they can guarantee specific delays. May be they will
become feasible a few years down the line.
cheers,
Neo
C
Colin Paul Gloster
Guest
In news:VT_Bh.45466$Gr2.31393@newssvr21.news.prodigy.net timestamped
Sun, 18 Feb 2007 16:10:29 GMT, "KJ" <kkjennings@sbcglobal.net> posted:
"<aravindcet2003@gmail.com> wrote in message
news:1171812965.260692.63090@q2g2000cwa.googlegroups.com...
Within the context of the VHDL language (and any other hardware description
language) 'synthesizable' is generally taken to mean something like "can be
transformed into a physical part". Whether a particular VHDL statement is
'synthesizable' or not depends on the technology planned to realize the
final 'physical part'. [..]
[..]"
Though something may literally be synthesizable given a particular
technology in a theoretical sense (if only we had a synthesis tool
which supported this part of the language...), practical usage of
the term "synthesizable" is also affected by the language features
supported by the synthesis tool in use. (Of course, you knew that
)
Sun, 18 Feb 2007 16:10:29 GMT, "KJ" <kkjennings@sbcglobal.net> posted:
"<aravindcet2003@gmail.com> wrote in message
news:1171812965.260692.63090@q2g2000cwa.googlegroups.com...
[..]
Within the context of the VHDL language (and any other hardware description
language) 'synthesizable' is generally taken to mean something like "can be
transformed into a physical part". Whether a particular VHDL statement is
'synthesizable' or not depends on the technology planned to realize the
final 'physical part'. [..]
[..]"
Though something may literally be synthesizable given a particular
technology in a theoretical sense (if only we had a synthesis tool
which supported this part of the language...), practical usage of
the term "synthesizable" is also affected by the language features
supported by the synthesis tool in use. (Of course, you knew that
)