Synthesizable (kind of) dual-edge FF

[Nicolas Matringe]

Hello
I have come up with this, which looks like a dual-edge FF but with some
limitations: it is not absolutely synchronous, and it can not handle
signal variations faster than the clock period but it still offers a
half-period resolution:

library ieee;
use ieee.std_logic_1164.all;

entity deff is
port (
d : in std_ulogic;
q : out std_ulogic;
clk : in std_ulogic;
rst : in std_ulogic);
end entity deff;

architecture rtl of deff is
signal qp : std_ulogic;
signal qn : std_ulogic;
signal qi : std_ulogic;
signal ck : std_ulogic;

begin

q <= qi;
ck <= qp xor qn;

process (clk, rst) is
begin -- process
if rst = '1' then
qp <= '0';
elsif rising_edge(clk) then
qp <= d;
end if;
end process;

process (clk, rst) is
begin -- process
if rst = '1' then
qn <= '0';
elsif falling_edge(clk) then
qn <= d;
end if;
end process;

process (rst, ck) is
begin -- process
if rst = '1' then
qi <= '0';
elsif rising_edge(ck) then
qi <= not qi;
end if;
end process;

end architecture rtl;

--
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| | | | | (_| |_| | Invalid return address: remove the -
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