synthesizable "after xx ns" statements

[Matt Boland]

Hi All,

I have read many times that the "after XX ns" delays are only available
for sims and are not synthesizable. I tried them in Xilinx ISE and they
synthesize OK.

Maybe they are just feeding through a know number of gates to get the delay?

I have only tried this on a CPLD, but I suppose it would work on FPGAs.
Does this really work on the device, or just in the sim? If it really
works, does anybody know the upper limit on the delay, or what the
accuracy is?

Is it limited to only Xilinx or is this common?

Thanks,

Matt Boland

 

No, timing parameters are not synthesizable by any synthesis tool. they
are used only for simulation purposes and synthesis tool ignores those
declarations.

-Neo

 

[Jezwold]

Have you looked at the post place and route simulation and seen all
the delays you specified?Thats not because the compiler inserted delays
in your code,its because of the propagation delays that your "after
xxx" statements where intended to model.

 

[Matt Boland]

Jezwold wrote:

Have you looked at the post place and route simulation and seen all
the delays you specified?Thats not because the compiler inserted delays
in your code,its because of the propagation delays that your "after
xxx" statements where intended to model.

Yeah, that's what I thought would be happening. It would be really cool
if they were synthesizable, even just small delays so that hold times
etc. would be easier to implement in a technologically independent way.

 

[Jezwold]

Part of the problem with that idea is that you would then introduce
hazards to the logic,which may or may nor cause the design to stop
working altogether.You can kind of introduce delays in the form of
redundant logic gates but it is a very bad design practice and most
compilers you have to mark them as not to be removed.

 

[Walid_gabadgi]

Hi,
Can I reply to you by a question ?
- why do you want to insert time delays during synthesis ?
Probably for 1 of 2 reasons :

* you want to meet your flip-flops setup time to avoid shoot-through
problems : Don't worry about it! all common synthesizers can solve this
problem by adding buffers
* You want to specify/force a certain delay for your in/outputs: also
don't worry, your can just specify constraints in your Design's pinouts
!

And this can be applied in ASIC or FPGA designs !

So, I don't think that for a reason, implementing "after xxx ns" is
useful in anyway.
Ciao Ciao

zingafriend@yahoo.com wrote:

No, timing parameters are not synthesizable by any synthesis tool.
they
are used only for simulation purposes and synthesis tool ignores
those
declarations.

-Neo