synthesising VHDL for Virtex2 using Xilinx ISE 6.1i

[Ashant]

Hi,

I have a VHDL model where a number of nodes are talking to each other
as well as a register file, using a common pair of address-data buses
with requests and acks for arbitration. Each node has a single process
with an FSM that governs its working.

The model works correctly in ModelSim, but I face problems when
synthesising. I am using the Xilinx ISE version 6.1i for this. The
synthesis phase completes, but XST throws a lot of warnings like the
one below:

WARNING:Xst:638 - in unit top_entity Conflict on KEEP property on
signal rfile_inst_Mtridata_data_bus<4> and
node2_inst_Mtridata_data_bus<4> node2_inst_Mtridata_data_bus<4> signal
will be lost.

"node2_inst" is an instance of a component called "node2" in an entity
called "top_entity". "data_bus" is an inout std_logic_vector port on
the node2 entity.

I had searched the newsgroups for similar problems and learned about
the "equivalent_register_removal" and "keep" attributes. But the
signal mentioned here, "Mtridata_data_bus" is inferred internally by
the synthesiser, so I have no idea how to set these attributes on this
signal! Setting this attribute for just "data_bus" doesn't seem to
help.

Inspite of these warnings, the synthesis phase finishes, but the
"translate" phase aborts after this error from NGDBUILD:

ERROR:NgdBuild:456 - logical net 'rfile_inst_Mtridata_data_bus<4>'
has both active and tristate drivers

I have no idea how to rectify this error. And this seems to occur only
for the Virtex and Spartan FPGAs ... I tried synthesising for the
CoolRunner CPLD, and everything worked out without any error.

How do I address this from my VHDL code? Or is this a tool or platform
specific problem?

Ashant.