synthesis...

[faz]

hai,

I learned from the Xilinx manual that for,while do statements are
synthesized in XST..

I would like to know how these statements(for,while,do while) are
implemented as logic design(EDIF and constraints) in FPGA device?? .

Though FOR loop is synthesizable , it is always advised that FOR loops
are not to be used in RTL coding. This is because it consumes lot of
resources (like area etc)whether XST will not optimize it before
targetting to FPGA device???

As wait() is not supported for synthesis wat should i use instead of
wait()??

regards,
faz

 

[Ralf Hildebrandt]

faz schrieb:

I learned from the Xilinx manual that for,while do statements are
synthesized in XST..

All loops are unrolled by the synthesis tools. So it depends on what you
model with a loop. Loops may be very handy to model some similar
objects. But remember: loops reduce the amount of typing. You should
always be able to code it without loops.
If you don't know what you have modeled with a loop then don't expect
anything for synthesis. It may be not synthesizable, may synthesize to
huge see of gates or to something very clever.

Ralf

 

[bigcaterpillar@gmail.com]

I give your a suggestion that you can read a book called "verilog HDL
synthesis A Parctical Primer" written J.Bhasker
I think synthesis is so important for logic design.

flypig

 

[faz]

On May 21, 5:18 am, "bigcaterpil...@gmail.com"
<bigcaterpil...@gmail.com> wrote:

I give your a suggestion that you can read a book called "verilog HDL
synthesis A Parctical Primer" written J.Bhasker
I think synthesis is so important for logic design.

flypig

hai,

it is always advised that FOR loops are not to be
used in RTL coding

for example:

for(int i=2; i>=0; i--) {
c+ = a*b[i+1];
};

In this case it is probably a much better idea to write a small
state
machine
for example:
case (state)
first:
begin
c+ = a[2]*b[3];
c+ = a[1]*b[2];
c+ = a[0]*b[1];
state=output;
end
.......

I would like to know the difference between number of clock
cycles,adders and multipliers required when "for" loop is used and
"state machine" is used??

Wat is the advantage i get interms of number of clocks,resources if i
have more number of states the above example is divided as 3 states
instead of 1 as follows.??

case (state)
first:
begin
c+ = a[2]*b[3];
state=second;
end
second:
begin
c+ = a[1]*b[2];
state=third;
end
third:
begin
c+ = a[0]*b[1];
state=output;
end

regards.
faz