synthesis

[Mike]

Can someone help me with the following question? Thanks!

Suppose A and B are mutually exclusive,
Is the following code synthesizable (i.e., will it cause race condition)?
If synthesizable, what will the gates look like?

always @ (posedge CLK)
begin
if (reset)
sig <= 0;
else
begin
if (A)
sig <= 1;

if (B)
sig <= 0;
end

end

 

[m]

On Fri, 04 Feb 2005 23:44:16 -0600, Mike <powermac@rogers.com> wrote:

Can someone help me with the following question? Thanks!

Suppose A and B are mutually exclusive,
Is the following code synthesizable (i.e., will it cause race condition)?
If synthesizable, what will the gates look like?

always @ (posedge CLK)
begin
if (reset)
sig <= 0;
else
begin
if (A)
sig <= 1;

if (B)
sig <= 0;
end

end

It's perfectly synthesizable and there will be no race conditions etc
because you put the non-blocking assignments into the same always
block; a case the order of which is well defined ie the last
assignment wins. The synthesizer doesn't know that they are mutually
exclusive so the logic will the the same as the following:

if (B)
sig <= 0;
else if (A)
sig <= 1;

So it will create a priority mux in gates but if A and B are exclusive
that won't matter.

 

[Mike]

mk<kal*@dspia.*comdelete> wrote in
news:l3p801l6n23mos660jscp1d6oaa78a4s7o@4ax.com:

On Fri, 04 Feb 2005 23:44:16 -0600, Mike <powermac@rogers.com> wrote:

Can someone help me with the following question? Thanks!

Suppose A and B are mutually exclusive,
Is the following code synthesizable (i.e., will it cause race
condition)? If synthesizable, what will the gates look like?

always @ (posedge CLK)
begin
if (reset)
sig <= 0;
else
begin
if (A)
sig <= 1;

if (B)
sig <= 0;
end

end

It's perfectly synthesizable and there will be no race conditions etc
because you put the non-blocking assignments into the same always
block; a case the order of which is well defined ie the last
assignment wins. The synthesizer doesn't know that they are mutually
exclusive so the logic will the the same as the following:

if (B)
sig <= 0;
else if (A)
sig <= 1;

So it will create a priority mux in gates but if A and B are exclusive
that won't matter.

Thank you very much! I really appreciate your answer!