Synthesis using Synplicity.

[kb33]

Hi,

I have the following code:

//IP_src_addr signal.....

reg [31:0] IP_src_addr,
IP_src_addr_comb;

//Flip-flop generation...

always @(negedge sys_clk)
begin
IP_src_addr <= #1 IP_src_addr_comb;
end


//Combinational Logic...

always @(reset_n or pkt_enab_n or byte_counter or pkt_in or
IP_src_addr)
begin

if(~reset_n)
begin
IP_src_addr_comb <= 0;

end

else
if(~pkt_enab_n)

casex (byte_counter)

34:
IP_src_addr_comb[31:24] <= pkt_in;

35:
IP_src_addr_comb[23:16] <= pkt_in;
36:
IP_src_addr_comb[15:8] <= pkt_in;
37:
IP_src_addr_comb[7:0] <= pkt_in;

default:
IP_src_addr_comb <= IP_src_addr;

endcase

else
IP_src_addr_comb <= 0;

end



When I try to synthesize this code with Synplicity, I get the following
error(for each one of the 32 bits of register IP_src_addr_comb) :

@W: CL118 kt_incom.v:303:5:303:6|Latch generated from always block
for signal IP_src_addr_comb, probably caused by a missing assignment in
an if or case stmt

I would like to know where I am making a mistake in the case statement
(or somewhere else) due to which this error is being generated.

Thanks,
Kanchan

 

[Jim Wu]

Not every bit in IP_src_addr_comb[31:0] is assinged in each branch of the
case statement.

HTH,
Jim

"kb33" <kanchan.devarakonda@gmail.com> wrote in message
news:1127517790.457729.221730@g49g2000cwa.googlegroups.com...

Hi,

I have the following code:

//IP_src_addr signal.....

reg [31:0] IP_src_addr,
IP_src_addr_comb;

//Flip-flop generation...

always @(negedge sys_clk)
begin
IP_src_addr <= #1 IP_src_addr_comb;
end


//Combinational Logic...

always @(reset_n or pkt_enab_n or byte_counter or pkt_in or
IP_src_addr)
begin

if(~reset_n)
begin
IP_src_addr_comb <= 0;

end

else
if(~pkt_enab_n)

casex (byte_counter)

34:
IP_src_addr_comb[31:24] <= pkt_in;

35:
IP_src_addr_comb[23:16] <= pkt_in;
36:
IP_src_addr_comb[15:8] <= pkt_in;
37:
IP_src_addr_comb[7:0] <= pkt_in;

default:
IP_src_addr_comb <= IP_src_addr;

endcase

else
IP_src_addr_comb <= 0;

end



When I try to synthesize this code with Synplicity, I get the following
error(for each one of the 32 bits of register IP_src_addr_comb) :

@W: CL118 kt_incom.v:303:5:303:6|Latch generated from always block
for signal IP_src_addr_comb, probably caused by a missing assignment in
an if or case stmt

I would like to know where I am making a mistake in the case statement
(or somewhere else) due to which this error is being generated.

Thanks,
Kanchan

 

[kb33]

Hi Jim,

For the bits that are not assigned in a particular branch of the case
statement, there is the default situation, so shouldn't that take care
of things? Do I have to explicitly assign some value to each bit in
every situation of the case statement?

Thanks,
Kanchan

 

[Bob Perlman]

On 23 Sep 2005 20:50:44 -0700, "kb33" <kanchan.devarakonda@gmail.com>
wrote:

Hi Jim,

For the bits that are not assigned in a particular branch of the case
statement, there is the default situation, so shouldn't that take care
of things? Do I have to explicitly assign some value to each bit in
every situation of the case statement?

Thanks,
Kanchan

The synthesis tool is trying to accommodate the behavior you
inadvertently specified.

In some branches, one or more bits are not being updated; by the
conventions of Verilog, those bits, being part of a reg, retain their
previous value. The synthesizer tries to generate hardware that also
retains the previous value for those bits, by inserting latches. As
for the default statement, it doesn't define the desired state of
unspecified bits in other branches.

Explicitly assign values to every bit in every branch, and your
problem--and error message--should go away.

Bob Perlman
Cambrian Design Works

 

[m]

On 23 Sep 2005 20:50:44 -0700, "kb33" <kanchan.devarakonda@gmail.com>
wrote:

Hi Jim,

For the bits that are not assigned in a particular branch of the case
statement, there is the default situation, so shouldn't that take care
of things? Do I have to explicitly assign some value to each bit in
every situation of the case statement?

Yes and the easiest way of doing that is to move the default condition
of the casex to the line before casex so that ...comb signal first
gets the default value and then you override with the calculated
values where needed. This way you have to specify only the specific
changes in each case situation.

 

[Jim Wu]

The "default" of the case statement is not the default value for bits that
are not assigned in other branches. Rather it's used when no other branches
are matched.

As someone already suggest, the following code should fix your problem:

if(~pkt_enab_n) begin
IP_src_addr_comb <= IP_src_addr;

casex (byte_counter)

34:
IP_src_addr_comb[31:24] <= pkt_in;

35:
IP_src_addr_comb[23:16] <= pkt_in;
36:
IP_src_addr_comb[15:8] <= pkt_in;
37:
IP_src_addr_comb[7:0] <= pkt_in;

default:
IP_src_addr_comb <= IP_src_addr;
endcase
....

HTH,
Jim

"kb33" <kanchan.devarakonda@gmail.com> wrote in message
news:1127533844.461508.77200@g49g2000cwa.googlegroups.com...

Hi Jim,

For the bits that are not assigned in a particular branch of the case
statement, there is the default situation, so shouldn't that take care
of things? Do I have to explicitly assign some value to each bit in
every situation of the case statement?

Thanks,
Kanchan

 

[Andy Peters]

kb33 wrote:

Hi,

I have the following code:

//IP_src_addr signal.....

reg [31:0] IP_src_addr,
IP_src_addr_comb;

//Flip-flop generation...

always @(negedge sys_clk)
begin
IP_src_addr <= #1 IP_src_addr_comb;
end


//Combinational Logic...

always @(reset_n or pkt_enab_n or byte_counter or pkt_in or
IP_src_addr)
begin

if(~reset_n)
begin
IP_src_addr_comb <= 0;

end

I would not expect this to create a proper asynchronous reset. It'll
add the reset condition to the flop's "D" input logic, making it
unnecessarily large.

Unless, of course, the intent was to create a synchronous reset.

-a