synthesis semantics vs. simulation semantics

[Choonho Root PLlab.]

Hi.
I am beginner of verilog language.
My question is
what is the difference of synthesis semantics vs. simulation semantics of verilog language.

 

[Neo]

Synthesis semantics are interpretted by sythesis tools to generate
hardware. simulation semantics are those which are interpretted by
simulators to perform simulation.
any construct simply dosent fall into either category neatly and there
is a lot of overlapping and it all depends on what you want to do, like
sythesize or simulate or both synthesize and simulate.