Synthesis related question - Please Help

[Daku]

Maybe this is inappropriate fro this group, I have a synthesis related
question. I am using Icarus Verilog 0.9.1 and I can synthesize my
design, resulting in a EDIF file. My question is what would be a good
tool that I can use for subsequent performance analysis.
Of course, I do not have access to any commercial tool.
Any hints, suggestions would be greatly appreciated.

 

[pallav]

On Nov 3, 9:11 am, Daku <dakup...@gmail.com> wrote:

Maybe this is inappropriate fro this group, I have a synthesis related
question. I am using Icarus Verilog  0.9.1 and I can synthesize my
design, resulting in a EDIF file. My question is what would be a good
tool that I can use for subsequent performance analysis.
Of course, I do not have access to any commercial tool.
Any hints, suggestions would be greatly appreciated.

I suppose you need to elaborate on what you mean by performance
analsysis. If you are using an FPGA, the vendors should be providing
tools for their boards. For ASIC, you need access to commercial tools.
There are some good/free back-end tools like Magic, Electric, LASI,
etc. There may be some academic tools available but they may have very
limited scope.

I'm not sure I would use Icarus Verilog for synthesis. There is also a
system called Alliance http://www-asim.lip6.fr/recherche/alliance/
that might helpful. Haven't used it.

 

[Petter Gustad]

pallav <pallavgupta@gmail.com> writes:

I'm not sure I would use Icarus Verilog for synthesis. There is also a
system called Alliance http://www-asim.lip6.fr/recherche/alliance/
that might helpful. Haven't used it.

Last time I used it (briefly, many years ago) it was VHDL only.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Daku]

Well, by performace I basically am interested in power, area and so
forth. Using Icarus, I have
generated the EDIF file. In the past, I have worked
with both Verilog and VHDL, and so that is not a
problem.
Could someone please provide some information on
the following ?
Do Magic, Electric and LASI accept EDIF format
input files, so that I can use my EDIF file as
input ?
Any hints, suggestions would be greatly appreciated. Thanks in advance
for your help.


On Nov 4, 7:50 am, pallav <pallavgu...@gmail.com> wrote:

On Nov 3, 9:11 am, Daku <dakup...@gmail.com> wrote:

Maybe this is inappropriate fro this group, I have a synthesis related
question. I am using Icarus Verilog 0.9.1 and I can synthesize my
design, resulting in a EDIF file. My question is what would be a good
tool that I can use for subsequent performance analysis.
Of course, I do not have access to any commercial tool.
Any hints, suggestions would be greatly appreciated.

I suppose you need to elaborate on what you mean by performance
analsysis. If you are using an FPGA, the vendors should be providing
tools for their boards. For ASIC, you need access to commercial tools.
There are some good/free back-end tools like Magic, Electric, LASI,
etc. There may be some academic tools available but they may have very
limited scope.

I'm not sure I would use Icarus Verilog for synthesis. There is also a
system called Alliancehttp://www-asim.lip6.fr/recherche/alliance/
that might helpful. Haven't used it.