Synthesis Problem

[Legalex]

I have this code written in verilog for a counter but my program xilinx is
14.1 finds 2 errors:

ERROR:Xst:899 - "numarator9.v" line 45: The logic for <counter_out> doe
not match a known FF or Latch template. The description style you are usin
to describe a register or latch is not supported in the current softwar
release.

ERROR:Xst:899 - "numarator9.v" line 44: The logic for <carry_out> does no
match a known FF or Latch template. The description style you are using t
describe a register or latch is not supported in the current softwar
release.

Can someone help me and tell me what's wrong about my code?

module counter9 (
clock ,
reset ,
enable ,
counter_out,
carry_out,
preset
);

input clock ;
input reset ;
input enable ;
input [3:0] preset;
output [3:0] counter_out ;
output carry_out;
wire clock ;
wire reset ;
wire enable ;
wire [3:0] preset;
reg [3:0] counter_out ;
reg carry_out;
reg a;


always @ (posedge clock or negedge reset)
begin : COUNTER
if (enable == 1'b1) begin
a<=1'b1;
end
else begin a<=1'b0;
end

if (reset == 1'b0) begin
counter_out <= preset;
carry_out<= 1'b0;
a<=1'b0;
end

else if (a == 1'b1) begin
counter_out <= counter_out - 1;
end

if(counter_out==4'b0)begin
carry_out<=~carry_out;
counter_out<= counter_out + 9;
end
else begin

carry_out<=1'b0;
end

end

endmodule



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[glen herrmannsfeldt]

Legalex <andreiopariuc@n_o_s_p_a_m.gmail.com> wrote:

I have this code written in verilog for a counter but my
program xilinx ise 14.1 finds 2 errors:

ERROR:Xst:899 - "numarator9.v" line 45: The logic for <counter_out> does
not match a known FF or Latch template. The description style you are using
to describe a register or latch is not supported in the current software
release.

ERROR:Xst:899 - "numarator9.v" line 44: The logic for <carry_out> does not
match a known FF or Latch template. The description style you are using to
describe a register or latch is not supported in the current software
release.

Can someone help me and tell me what's wrong about my code?

(snip)

First, the indenting is very confusing.

always @ (posedge clock or negedge reset)

So, asynchronous reset, since it is in the sensitivity list.

begin : COUNTER
if (enable == 1'b1) begin
a<=1'b1;
end
else begin a<=1'b0;
end

But it is dependent on enable? I believe you can have either
asynchronous or synchronous reset, but not some of each.

if (reset == 1'b0) begin
counter_out <= preset;
carry_out<= 1'b0;
a<=1'b0;
end

Try to make a very simple counter, with either asynchronous or
synchronous reset, and a count enable. It has to match what the
real FF's in the real FPGAs do.

else if (a == 1'b1) begin
counter_out <= counter_out - 1;
end

if(counter_out==4'b0)begin
carry_out<=~carry_out;
counter_out<= counter_out + 9;
end
else begin

carry_out<=1'b0;
end

-- glen

 

[Legalex]

this should be a 4 bit down counter with asyncronous reset(0 active),wit
an enable that plays the role of a 'start' for the counter(that's why
chose to change the value of "a" depending on enable because enable isn'
always "1"->in my project enable= out_of_a_clock_devider & out of a DF
which has as inputs "start" and "stop")
I just can't make this counter work..in modelsim everything is fine...
If anyone knows how to fix it..please help me...

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[Legalex]

this should be a 4 bit down counter with asyncronous reset(0 active),with
an enable that plays the role of a 'start' for the counter(that's why I
chose to change the value of "a" depending on enable because enable isn't
always "1"->in my project enable= out_of_a_clock_devider & out of a DFF
which has as inputs "start" and "stop")
I just can't make this counter work..in modelsim everything is fine...
If anyone knows how to fix it..please help me...

---------------------------------------
Posted through http://www.FPGARelated.com

I forgot to say that when I reset it, the counter has to take the prese

value and start countering from that value - that's why I have a prese
there.

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[glen herrmannsfeldt]

Legalex <andreiopariuc@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

this should be a 4 bit down counter with asyncronous reset(0 active),with
an enable that plays the role of a 'start' for the counter(that's why I
chose to change the value of "a" depending on enable because enable isn't
always "1"->in my project enable= out_of_a_clock_devider & out of a DFF
which has as inputs "start" and "stop")

I think part of the problem related to enable.

It is hard to follow the logic through a, and maybe the tools also
can't figure that out, but you don't want enable to apply to the
reset, otherwise it isn't an asynch reset. I think that is part of
the problem. You might also need enable in the sensitivity list,
otherwise, and being inside the always block, the assignment to a
is also a register. Actually, remove a. Just do all the assignments
based on clock, reset, and enable, and be sure that reset applies
independent of clock and enable.

-- glen

 

[Legalex]

In modelsim it worked with testbench and all..the results were good

I re-wrote the code like this but it still gives me those errors

module counter9 (
clock ,
reset ,
enable ,
counter_out,
carry_out,
preset
);

input clock ;
input reset ;
input enable ;
input [3:0] preset;
output [3:0] counter_out ;
output carry_out;
wire clock ;
wire reset ;
wire enable ;
wire [3:0] preset;
reg [3:0] counter_out ;
reg carry_out;



always @ (posedge clock or negedge reset or posedge enable)
begin : COUNTER


if (reset == 1'b0) begin
counter_out <= preset;
carry_out<= 1'b0;
end

else if (enable == 1'b1) begin
counter_out <= counter_out - 1;


if(counter_out==4'b0)begin
carry_out<=~carry_out;
counter_out<= counter_out + 9;
end
else begin

carry_out<=1'b0;
end
end

end
endmodule

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[Andy]

On May 16, 12:42 am, "Legalex"
<andreiopariuc@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

this should be a 4 bit down counter with asyncronous reset(0 active),with
an enable that plays the role of a 'start' for the counter(that's why I
chose to change the value of "a" depending on enable because enable isn't
always "1"->in my project enable= out_of_a_clock_devider & out of a DFF
which has as inputs "start" and "stop")
I just can't make this counter work..in modelsim everything is fine...
If anyone knows how to fix it..please help me...

---------------------------------------
Posted throughhttp://www.FPGARelated.com

I forgot to say that when I reset it, the counter has to take the preset
value and start countering from that value - that's why I have a preset
there.

---------------------------------------
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Does your target device allow presetting to a variable (non-constant)
value? (probably not).

Follow the templates in the user guide, at least until you get a
better idea of what works and what does not.

Your enable and reset logic is messed up. Think about priorities of
inputs. (e.g. highest priority is reset, second is (clocked) enable,
etc.) Code accordingly (e.g. if-else). For example, you reset, but
then you run other code that affects those same outputs, negating the
effect of reset.

When you say it is fine in modelsim, did you actually simulate it
(thoroughly) and the results are good, or did you just compile it?
This is not a language issue (modelsim compiles it), it is an issue
where you are not properly describing the behavior of hardware that
can be constructed in your target FPGA.

Andy

 

[Anssi Saari]

"Legalex" <andreiopariuc@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes:

this should be a 4 bit down counter with asyncronous reset(0 active),with
an enable that plays the role of a 'start' for the counter(that's why I
chose to change the value of "a" depending on enable because enable isn't
always "1"...

So how does assigning 'enable' to 'a' synchronously make enable work
like 'start'? If enable is a pulse that should make the counter run
forever then I don't think you have the right logic for that.

As for the little synthesis problem(s), you describe a counter that can
both decrement the counter and increment by 9, at the same time. Fairly
exotic hardware, that. Similar thing with a. Hence the error message
from XST.

This is why logic is usually described so that you have one top level if
in an always block. One branch for reset, the other for the interesting
stuff. Within the same level in an if structure you can contradict your
assignments to your heart's content and the last one will be in force at
the end of the clock cycle. Just be sure that's what you wanted.

 

[Ed McGettigan]

On May 16, 6:03 am, "Legalex"
<andreiopariuc@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

In modelsim it worked with testbench and all..the results were good

I re-wrote the code like this but it still gives me those errors

module counter9 (
  clock ,
  reset ,
  enable ,
  counter_out,
  carry_out,
  preset
  );

  input  clock ;
  input reset ;
  input enable ;
  input [3:0] preset;
  output [3:0] counter_out ;
  output carry_out;
  wire clock ;
  wire reset ;
  wire enable ;
  wire [3:0] preset;
  reg [3:0] counter_out ;
  reg carry_out;

  always @ (posedge clock or negedge reset or posedge enable)
  begin : COUNTER

        if (reset == 1'b0) begin
      counter_out <=  preset;
      carry_out<= 1'b0;
    end

    else if (enable == 1'b1) begin
      counter_out <=   counter_out - 1;

 if(counter_out==4'b0)begin
 carry_out<=~carry_out;
    counter_out<= counter_out + 9;
    end
    else begin

    carry_out<=1'b0;
    end
         end

  end
endmodule

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Your problem is that you are not creating code that can be mapped into
standard register logic. In this latest version you have a clock,
asynchronous enable and a dyanmic asynchronous reset/preset and this
doesn't exist in the real world.

As a first step towards writing robust and easily timed code avoid the
use of asynchronous resets/presets unless they are absolutely
necessary and use a synchronous reset/preset instead.

---- Code Begin ----
always @ (posedge clock)
begin : COUNTER

if (reset == 1'b0) begin
counter_out <= preset;
carry_out <= 1'b0;
end
else if (enable == 1'b1) begin
if (counter_out == 4'b0) begin
counter_out <= 9;
carry_out <= 1'b1;
end
else begin
counter_out <= counter_out - 1;
carry_out <= 1'b0;
end
end
end
----- Code End -----

Ed McGettigan
--
Xilinx Inc.