Synthesis -> Physical Layout

K

KaRtiK

Guest
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

I want to compare layouts of different designs and study the tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
 
"KaRtiK" <kkrishnan@wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32@posting.google.com...
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Click to expand...

Cherrs
Jer
 
What tool set u have? Depending on that I can tell u how to do this.

-zk

"Jerry" <nospam@nowhere.com> wrote in message news:<101m0f23tpce1d0@corp.supernews.com>...
"KaRtiK" <kkrishnan@wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32@posting.google.com...
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII

Cherrs
Jer
Click to expand...
 
Hello

I have the entire setup of Cadence,Synopsys,Xilinx and Mentor Graphics
tools in my Research lab.

I have synthesized my code using Design compiler.and wondering what
would be the design flow if I need to generate a layout a Cadence.

Thanks

Kartik

www.cae.wisc.edu/~kartik






zpalak@yahoo.com (Z) wrote in message news:<ede4169e.0402061120.4a06ffd3@posting.google.com>...
What tool set u have? Depending on that I can tell u how to do this.

-zk

"Jerry" <nospam@nowhere.com> wrote in message news:<101m0f23tpce1d0@corp.supernews.com>...
"KaRtiK" <kkrishnan@wisc.edu> wrote in message
news:11510c1b.0401301311.3ca40b32@posting.google.com...
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

I want to compare layouts of different designs and study the
tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII

Cherrs
Jer
Click to expand...
 
I do my synthesis using design compiler
and then port my netlist into Silicon Ensemble . You need to import
the netlist and the timing information ( sdf ) into SE. You can then
proceed to do your
flow like clock tree synthesis, power bussing and routing..
hope it helps..
Sachin
 
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