Synthesis parameter check

[mjl296@hotmail.com]

Hi,

I have a parameterisable module and I would like to perform a sanity
check on the range of the parameters. For simulation I might do this:

generate
if (P_PARAM != 1)
begin
//synthesis translate_off
initial
begin
$display("P_PARAM out of range");
$stop;
end
//synthesis translate_on
end
endgenerate

Does anyone have a recommendation for a good way of getting the
synthesis tool to catch the parameterisation error as well?

Thanks.

 

[Amal]

Why not use an assert statement:

// pragma translate_off
assert ( P_PARAM == 1 ) else $error( "P_PARAM out of range" );
// pragma translate_on

-- Amal

On May 16, 4:50 am, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

Hi,

I have a parameterisable module and I would like to perform a sanity
check on the range of the parameters. For simulation I might do this:

generate
if (P_PARAM != 1)
begin
//synthesis translate_off
initial
begin
$display("P_PARAM out of range");
$stop;
end
//synthesis translate_on
end
endgenerate

Does anyone have a recommendation for a good way of getting the
synthesis tool to catch the parameterisation error as well?

Thanks.

 

[Jonathan Bromley]

On Fri, 16 May 2008 01:50:17 -0700 (PDT),
<mjl296@hotmail.com> wrote:

I have a parameterisable module and I would like to perform a sanity
check on the range of the parameters.
[...]
Does anyone have a recommendation for a good way of getting the
synthesis tool to catch the parameterisation error as well?

Use VHDL!

Another reason why VHDL is superior to Verilog as an RTL
language: it has always supported assertions over constants,
and any decent synthesis tool will check such assertions
at elaboration.

There is, at long last, a proposal on the table to add
elaboration-time assertions to SystemVerilog. Don't hold
your breath; it'll be years before it's available.

Yours in grumpiness
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Fri, 16 May 2008 13:48:15 -0700 (PDT), Amal wrote:

I have a parameterisable module and I would like to perform a sanity
check on the range of the parameters. For simulation I might do this:
[...]
Does anyone have a recommendation for a good way of getting the
synthesis tool to catch the parameterisation error as well?

Why not use an assert statement:
// pragma translate_off
[...]

That ain't going to work too well at synthesis time!

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kevin Neilson]

Jonathan Bromley wrote:

On Fri, 16 May 2008 01:50:17 -0700 (PDT),
mjl296@hotmail.com> wrote:

I have a parameterisable module and I would like to perform a sanity
check on the range of the parameters.
[...]
Does anyone have a recommendation for a good way of getting the
synthesis tool to catch the parameterisation error as well?

Use VHDL!

Another reason why VHDL is superior to Verilog as an RTL
language: it has always supported assertions over constants,
and any decent synthesis tool will check such assertions
at elaboration.

There is, at long last, a proposal on the table to add
elaboration-time assertions to SystemVerilog. Don't hold
your breath; it'll be years before it's available.

Yours in grumpiness

And it requires three times the lines of code, making you look much more
productive!

Seriously, I think XST supports $display(), so you could display an
error to the console, although you mightn't be able to halt synthesis.
I'm not sure if other synthesizers support this.
-Kevin