Synthesis of reg with initial value

[googler]

In my RTL (DUT) I have something like this:
trireg (medium) PAD;
reg [1:0] pad_delay = 2'b00;
bufif1 #pad_delay (PAD, abc, xyz);

The reason I have pad_delay defined as a reg is because for some tests
I am forcing it to 2'b01 from inside the test. But for most other
tests, I would like to have it as 2'b00, which is why it has been
initialized to 2'b00 in the above code. My question is, is this a
right thing to do? The simulations are working fine, but I am not sure
if the initialization of pad_delay to 2'b00 will happen when it
undergoes synthesis. And if that does not happen, then I suppose
pad_delay will have the value 'X' and things will go wrong. Please let
me know if I am correct in thinking this, or if the above code does
not have this problem. If the above is not correct, then what is a
right way to do it?

Thanks for any input.

PS:
As an aside, I want to add this too. At first I had pad_delay as
'parameter':
parameter [1:0] pad_delay = 2'b00;
This worked fine for one simulation, but after that I started getting
load error in Modelsim, which complained that a 'force' statement
cannot be executed on 'parameter' object (which I am doing in a few
tests). So I changed 'parameter' to 'reg'. Strange, but as I observed,
the simulator behaved differently on two different runs.

 

[gabor]

On Apr 10, 6:30 pm, "googler" <pinaki_...@yahoo.com> wrote:

In my RTL (DUT) I have something like this:
trireg (medium) PAD;
reg [1:0] pad_delay = 2'b00;
bufif1 #pad_delay (PAD, abc, xyz);

The reason I have pad_delay defined as a reg is because for some tests
I am forcing it to 2'b01 from inside the test. But for most other
tests, I would like to have it as 2'b00, which is why it has been
initialized to 2'b00 in the above code. My question is, is this a
right thing to do? The simulations are working fine, but I am not sure
if the initialization of pad_delay to 2'b00 will happen when it
undergoes synthesis. And if that does not happen, then I suppose
pad_delay will have the value 'X' and things will go wrong. Please let
me know if I am correct in thinking this, or if the above code does
not have this problem. If the above is not correct, then what is a
right way to do it?

Thanks for any input.

PS:
As an aside, I want to add this too. At first I had pad_delay as
'parameter':
parameter [1:0] pad_delay = 2'b00;
This worked fine for one simulation, but after that I started getting
load error in Modelsim, which complained that a 'force' statement
cannot be executed on 'parameter' object (which I am doing in a few
tests). So I changed 'parameter' to 'reg'. Strange, but as I observed,
the simulator behaved differently on two different runs.

Since no one else has touched this yet I'll put my 2 cents in...

ModelSim cannot "force" a parameter because it is evaluated at
compile-time just like for example a `define. If you need the
delay value to change during a portion of the simulation it
needs to be dynamic like the variable (reg) you defined.

If you use a parameter, you can change the value at compile time
without editing your source file by using +define+ in the vlog
command. This will require re-starting the simulation.

If you really want to synthesize your code with the variable
delay parameter, you need to think about what hardware the
synthesis tool can instantiate that does this. Generally
sythesis will ignore # delays anywhere in your source. These
are generally used for simulation only. If you need a delay
in your design you need to understand the underlying hardware
and instantiate an appropriate delay element.

HTH,
Gabor