synthesis of memory construct

[Ani]

hi

i have included a statement of the form reg [7:0] memory [0:65536] and
later accessed various locations in this memory
using memory[1], memory[n] etc. Is this type of code synthesizable?
MAGMA is NOT showing any errors but is unable
to complete the synthesis anyway. Please help.

Thanks
ruddha

 

[Utku Özcan]

Your coding style might affect how the tool infers memory effectively.
Don't try to read or write the memory in several places in an always
block.
In that case synthesis tool might not understand what you want.

Try to access the memory only in two places, ie. in two separate
always blocks:

always @(posedge clk)
begin: READ_MEMORY
data_out <= memory [addr];
end

always @(posedge clk)
begin: WRITE_MEMORY
memory [addr] <= data_in;
end

Then do use the data_in, data_out, in completely other always blocks.
This way you isolate the memory out of logic. It might dramatically
help your synthesizer to "understand" that you are modelling a memory.

On the other side, if you are using a special technology, always use a
pre-compiled RAM macro.
It might dramatically reduce your synthesis runtime (both the generic
synthesis and technology mapping) and get better results.

Utku

On Feb 21, 12:31 pm, "Ani" <aniruddha.ud...@gmail.com> wrote:

hi

i have included a statement of the form reg [7:0] memory [0:65536] and
later accessed various locations in this memory
using memory[1], memory[n] etc. Is this type of code synthesizable?
MAGMA is NOT showing any errors but is unable
to complete the synthesis anyway. Please help.

Thanks
ruddha

 

[Utku Özcan]

Additional note:

you might need to use "chip select", "read enable" or "write enable"
signals additionally in the said always blocks. If you need to model 2
or even 3 port memory, the modelling below might be a little
different. Please refer to synthesizer manuals. They might have
examples.

But the main idea is what I wrote in the posting below.

Utku.

On Feb 21, 1:57 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote:

Your coding style might affect how the tool infers memory effectively.
Don't try to read or write the memory in several places in an always
block.
In that case synthesis tool might not understand what you want.

Try to access the memory only in two places, ie. in two separate
always blocks:

always @(posedge clk)
begin: READ_MEMORY
data_out <= memory [addr];
end

always @(posedge clk)
begin: WRITE_MEMORY
memory [addr] <= data_in;
end

Then do use the data_in, data_out, in completely other always blocks.
This way you isolate the memory out of logic. It might dramatically
help your synthesizer to "understand" that you are modelling a memory.

On the other side, if you are using a special technology, always use a
pre-compiled RAM macro.
It might dramatically reduce your synthesis runtime (both the generic
synthesis and technology mapping) and get better results.

Utku

On Feb 21, 12:31 pm, "Ani" <aniruddha.ud...@gmail.com> wrote:

hi

i have included a statement of the form reg [7:0] memory [0:65536] and
later accessed various locations in this memory
using memory[1], memory[n] etc. Is this type of code synthesizable?
MAGMA is NOT showing any errors but is unable
to complete the synthesis anyway. Please help.

Thanks
ruddha

 

[John_H]

Ani wrote:

hi

i have included a statement of the form reg [7:0] memory [0:65536] and
later accessed various locations in this memory
using memory[1], memory[n] etc. Is this type of code synthesizable?
MAGMA is NOT showing any errors but is unable
to complete the synthesis anyway. Please help.

Thanks
ruddha

Another thought: define the memory as 2^n depth. The 0:65536 is one
over. Perhaps you meant 0:65535? The latter is appropriate for a 16
bit address vector.

A half megabit memory is rather large. Perhaps it would be better to
use a primitive from your ASIC libraries if MAGMA is having speed issues.

 

[mk]

On 21 Feb 2007 03:31:14 -0800, "Ani" <aniruddha.udipi@gmail.com>
wrote:

hi

i have included a statement of the form reg [7:0] memory [0:65536] and
later accessed various locations in this memory
using memory[1], memory[n] etc. Is this type of code synthesizable?
MAGMA is NOT showing any errors but is unable
to complete the synthesis anyway. Please help.

Thanks
ruddha

This is legal verilog so there should be no errors but for ASIC
synthesis (assuming this but Magma has fpga synthesis too so you need
to clarify) there is no memory infering so you're getting half a meg
of registers so magma maybe hitting a capacity problem here. Try using
a memory compiler to generate the storage you need instead of
registers. Another option might be using the register file cells which
might exist in your standard cell library (RFxxx?). You can construct
your storage out of these instead of the flops. If you insist on using
flops for this much storage you need to consider what your clock tree
is going to look like too.