Synthesis of initialized array?

[Brandon]

I would like to have 'coeff_height_c' coefficients read from a text
file to be stored into a signal array of type std_logic_vector. The slv
will serve as a LUT, which I need to access during runtime.

I haven't written anything yet, but I'd probably have a function to
initialize a signal using the known bit width, height, and filename to
read the coefficients from. I'd like the signal 'coeff_lut' to
synthesize as a static array. That way it will be constructed as a LUT
in translation to the FPGA. Will this exhibit the bheavior I want? I
want to do this so I can have some coefficient files that can be
generated in Matlab (for example) very easily. I do not want other
engineers to have to monkey with editing a vhdl package file to change
some values around.

type arrayofslv_t is array (natural range <&gt of
std_logic_vector(coeff_width_c-1 downto 0);

signal coeff_lut: arrayofslv_t(coeff_height_c-1downto 0) :=
init_slv_array(coeff_width_c, coeff_height_c, coeff_file_name_c);

Note: the function call would probably read in a text file containing
types real (floating point) using text i/o, convert them to binary and
put them into an array, which is the returned output of the function.

Thanks,
-Brandon

 

[Brandon]

Btw, I'm using Xilinx XST for synthesis.