Synthesis of galois adder

[Patrick]

hello everybody,

When I synthesise this component under Quartus 4.1 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add_galois is
port(
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(7 downto 0)
);
end add_galois;

architecture plus of add_galois is
begin
OUEX:for i in 0 to 7 generate c(i)<=a(i) xor b(i); end
generate;
end plus;

Quartus implemente this with 8 logic element, OK.

When I use this add_galois in an other design, Quartus takes 87 logic
element per add_galois !!!!

And when I visualise the add_galois in RTL Viewer, there's only 8 XOR
per add_galois !!!

What's happen ?

 

[Paul Uiterlinden]

Patrick wrote:

hello everybody,

When I synthesise this component under Quartus 4.1 :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add_galois is
port(
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(7 downto 0)
);
end add_galois;

architecture plus of add_galois is
begin
OUEX:for i in 0 to 7 generate
c(i)<=a(i) xor b(i);
end generate;
end plus;

Quartus implemente this with 8 logic element, OK.

When I use this add_galois in an other design, Quartus takes 87 logic
element per add_galois !!!!

And when I visualise the add_galois in RTL Viewer, there's only 8 XOR
per add_galois !!!

What's happen ?

I have no idea, never worked with Quartus. Seems to be a quirck in
Quartus which has nothing to do with VHDL. The only thing I can say is
that you don't need to use a generate loop here. Just write:

OUEX: c <= a xor b;

And as far I am concerned, I would not bother to create an entity for
such a simple construction.

Paul.