Synthesis of for-loops

[LYY]

Suppose I want to assignan signals between 2 arrays:

reg [datawidth-1:0] a[0:length-1];
reg [datawidth-1:0] b[0:length-1];

always @(posedge clk) begin
b[0] <= a[0];
b[1] <= a[1];
b[2] <= a[2];
............
b[length-1] <= a[length-1];
end

This requires a lot of typing and is not as maintainable as a for-loop
version:

integer i;
reg [datawidth-1:0] a[0:length-1];
reg [datawidth-1:0] b[0:length-1];

always @(posedge clk) begin
for (i = 0; i<datawidth; i=i+1) begin
b <= a;
end
end

However, my concern is whether the 2 versions will produce the same
amount of logic across different synthesis tools. Will the for-loop
version introduce the overhead of a counter?
Will the for-loop version result in sequential logic across the
assignment which cause more delays as compared to the parallel
assignment(1st) version?

YY

 

[mjl296@hotmail.com]

I assume that you want to assign length elements, each of width
datawidth, so your loop should read:

always @(posedge clk) begin
for (i = 0; i<length; i=i+1) begin
b <= a;
end
end

If this is the case, then the two structures should produce the same
circuit. Both structures should infer datawidth*length registers. The
for loop will be unrolled by the synthesis tool and will not result in
a physical counter.

In my experience, this use of a for loop is common in synthesisable
code and should not worry you.

Cheers,

Mark




LYY wrote:

Suppose I want to assignan signals between 2 arrays:

reg [datawidth-1:0] a[0:length-1];
reg [datawidth-1:0] b[0:length-1];

always @(posedge clk) begin
b[0] <= a[0];
b[1] <= a[1];
b[2] <= a[2];
............
b[length-1] <= a[length-1];
end

This requires a lot of typing and is not as maintainable as a for-loop
version:

integer i;
reg [datawidth-1:0] a[0:length-1];
reg [datawidth-1:0] b[0:length-1];

always @(posedge clk) begin
for (i = 0; i<datawidth; i=i+1) begin
b <= a;
end
end

However, my concern is whether the 2 versions will produce the same
amount of logic across different synthesis tools. Will the for-loop
version introduce the overhead of a counter?
Will the for-loop version result in sequential logic across the
assignment which cause more delays as compared to the parallel
assignment(1st) version?

YY