synthesis of comparison operators

Hi All,
I was wondering how operators like "less than", "less than or equal
to", etc are synthesized.
E.g.:
sig_x = '1' when siga >= sigb else '0'
with siga and sigb are 8 bit vectors
Is it done with full adders, subtracting sigb from siga, or is it done
in another way.
Kind regards, Wim

 

[Mike Treseler]

sybhs@yahoo.com wrote:

I was wondering how operators like "less than", "less than or equal
to", etc are synthesized.

sig_x = '1' when siga >= sigb else '0'
with siga and sigb are 8 bit vectors
Is it done with full adders, subtracting sigb from siga, or is it done
in another way.

In the code, it's done using numeric_std functions
and signed, unsigned, natural and integer types.
http://www.csee.umbc.edu/help/VHDL/packages/numeric_std.vhd

In synthesis, it's done with gates.
Find or write an example entity and run synthesis.
View the RTL and Technology schematics.

-- Mike Treseler