synthesis of black box modules

[zhaoke]

hello, everyone,
i am now working with synplify pro.and i have a program with 3 component as
black box.
but now there are 3 warning : unbound component mapped to black box.and when
i
use technology view, there is no ports and instances.
i do not know what is the matter.
Any replies greatly appreciated.
thanks
zhaoke

my program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test is
end test;

architecture Behavioral of test is
component ARM7 is
port ( ADR : out std_logic_vector(23 downto 0);
DAT : inout std_logic_vector(15 downto 0);
OE, WR0, CSEXT2, CSEXT3 : out std_logic
);

end component;
component OSCI is
port( CLK : out std_logic
);
end component;
component myfpga is
port( A : in std_logic_vector(23 downto 0);
D : inout std_logic_vector(15 downto 0);
OE , WR0, CSEXT2, CSEXT3 : in std_logic;
CLK : in std_logic);
end component;
signal ADRS : std_logic_vector(23 downto 0);
signal DATS : std_logic_vector(15 downto 0);
signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic;
begin
my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S);
my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS);
my_osci : OSCI port map(CLKS);

end Behavioral;

 

[Yardi]

try writing a wrapper HDL file for each of your components. the
wrapper file will act as a dummy upper-level file for these
components. you can have the same pin names (but different entity
name) for the wrapper file. then use the wrapper file entity
declaration in this HDL file as a component

"zhaoke" <zhaoke@eikon.tum.de> wrote in message news:<bfgasq$kci$1@wsc10.lrz-muenchen.de>...

hello, everyone,
i am now working with synplify pro.and i have a program with 3 component as
black box.
but now there are 3 warning : unbound component mapped to black box.and when
i
use technology view, there is no ports and instances.
i do not know what is the matter.
Any replies greatly appreciated.
thanks
zhaoke

my program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test is
end test;

architecture Behavioral of test is
component ARM7 is
port ( ADR : out std_logic_vector(23 downto 0);
DAT : inout std_logic_vector(15 downto 0);
OE, WR0, CSEXT2, CSEXT3 : out std_logic
);

end component;
component OSCI is
port( CLK : out std_logic
);
end component;
component myfpga is
port( A : in std_logic_vector(23 downto 0);
D : inout std_logic_vector(15 downto 0);
OE , WR0, CSEXT2, CSEXT3 : in std_logic;
CLK : in std_logic);
end component;
signal ADRS : std_logic_vector(23 downto 0);
signal DATS : std_logic_vector(15 downto 0);
signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic;
begin
my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S);
my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS);
my_osci : OSCI port map(CLKS);

end Behavioral;