Synthesis issues in Merkle Hellman Knapsack Cryptosystems

G

Gandalf

Guest
Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a random number generator but I'm stuck on the Transmitter part. I've written this code :
entity Knapsack_Tx is
port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic;
data:std_logic_vector;cip:eek:ut std_logic_vector(7 downto 0));
end Knapsack_Tx;


architecture Encipher of Knapsack_Tx is

type rndnum is array(7 downto 0) of std_logic;
type easy is array(7 downto 0) of std_logic;
--type index is array (0 to 7) of integer;




function elf(rnum:rndnum) return easy is

variable knap1:easy;
variable i: integer := 0;
variable rnum1 : rndnum :=rnum;
variable int1, int2 :integer :=0;

begin

int1:= to_integer(rnum1(i-1));
int2:= to_integer(rnum1(i));

for i in 0 to 7 loop
if int1 <= int2 then
knap1(i) := rnum1(i);
end if;
end loop;

return knap1;

end function elf;

begin


end architecture Encipher;

The rnum1 variable is an array which is used to store the random values obtained from the RNG. The code is obviously incomplete but essentially it revolves around this. Check Syntax reveals that to_integer is not recognised. If anyone can help it would be nice :)
 
On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote:
Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a random number generator but I'm stuck on the Transmitter part. I've written this code :

entity Knapsack_Tx is

port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic;

data:std_logic_vector;cip:eek:ut std_logic_vector(7 downto 0));

end Knapsack_Tx;





architecture Encipher of Knapsack_Tx is



type rndnum is array(7 downto 0) of std_logic;

type easy is array(7 downto 0) of std_logic;

--type index is array (0 to 7) of integer;









function elf(rnum:rndnum) return easy is



variable knap1:easy;

variable i: integer := 0;

variable rnum1 : rndnum :=rnum;

variable int1, int2 :integer :=0;



begin



int1:= to_integer(rnum1(i-1));

int2:= to_integer(rnum1(i));



for i in 0 to 7 loop

if int1 <= int2 then

knap1(i) := rnum1(i);

end if;

end loop;



return knap1;



end function elf;



begin





end architecture Encipher;



The rnum1 variable is an array which is used to store the random values obtained from the RNG. The code is obviously incomplete but essentially it revolves around this. Check Syntax reveals that to_integer is not recognised.. If anyone can help it would be nice :)
Click to expand...

First of all, why are you creating an array of std_logic? Just use a std_logic_vector. You should be including std_logic_1164 package file.

Once that's complete, use the numeric_std package file for your math.
Your conversion will be:
output <= to_integer(unsigned(input_slv));

Read more about how to convert std_logic_vector to integer and why using std_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html
 
On Wednesday, July 2, 2014 9:29:26 PM UTC+5:30, Russell wrote:
On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote:

Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a random number generator but I'm stuck on the Transmitter part. I've written this code :



entity Knapsack_Tx is



port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic;



data:std_logic_vector;cip:eek:ut std_logic_vector(7 downto 0));



end Knapsack_Tx;











architecture Encipher of Knapsack_Tx is







type rndnum is array(7 downto 0) of std_logic;



type easy is array(7 downto 0) of std_logic;



--type index is array (0 to 7) of integer;



















function elf(rnum:rndnum) return easy is







variable knap1:easy;



variable i: integer := 0;



variable rnum1 : rndnum :=rnum;



variable int1, int2 :integer :=0;







begin







int1:= to_integer(rnum1(i-1));



int2:= to_integer(rnum1(i));







for i in 0 to 7 loop



if int1 <= int2 then



knap1(i) := rnum1(i);



end if;



end loop;







return knap1;







end function elf;







begin











end architecture Encipher;







The rnum1 variable is an array which is used to store the random values obtained from the RNG. The code is obviously incomplete but essentially it revolves around this. Check Syntax reveals that to_integer is not recognised. If anyone can help it would be nice :)



First of all, why are you creating an array of std_logic? Just use a std_logic_vector. You should be including std_logic_1164 package file.



Once that's complete, use the numeric_std package file for your math.

Your conversion will be:

output <= to_integer(unsigned(input_slv));



Read more about how to convert std_logic_vector to integer and why using std_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html
Click to expand...

Hey Thanks, But I need several random numbers in my array so that a private key may be derived. The module is connected to a random number generator which generates a std_logic_vector of 8 bits.
 
Gandalf wrote:

Hey Thanks, But I need several random numbers in my array so that a
private key may be derived. The module is connected to a random
number generator which generates a std_logic_vector of 8 bits.
Click to expand...

Then you need an array of std_logic_vectors, not an array of std_logic.

Right now what you're doing here:

int1:= to_integer(rnum1(i-1));

.... is accessing a single bit in a std_logic_vector. Not sure how useful
it is to convert a single bit to an integer. I suppose you expect
rnum1(i-1) to be a random number of 8 bits length instead?

You probably want to declare "rndnum" and "easy" as arrays of
std_logic_vectors(7 downto 0) to be able to store incoming rnum values
or something. I have no idea about the algorithm, so I'm guessing here...

Besides, a std_logic or a std_logic_vector is not a numerical value,
it's a bit or a collection of bits. That's why you cannot convert it to
integer. You either have to declare the elements of your rnum1 array as
some sort of numerical value (for example unsigned(7 downto 0)) or you
have to cast before trying to convert:

int1:= to_integer(unsigned(rnum1(i-1)));

(or maybe signed, depending on what values that random number generator
delivers). The whole conversion doesn't make a whole lot of sense if
what you're converting is a single it, though.

HTH,
Sean
 
On Thursday, July 3, 2014 3:35:01 PM UTC+5:30, Sean Durkin wrote:
Gandalf wrote:



Hey Thanks, But I need several random numbers in my array so that a

private key may be derived. The module is connected to a random

number generator which generates a std_logic_vector of 8 bits.



Then you need an array of std_logic_vectors, not an array of std_logic.



Right now what you're doing here:



int1:= to_integer(rnum1(i-1));



... is accessing a single bit in a std_logic_vector. Not sure how useful

it is to convert a single bit to an integer. I suppose you expect

rnum1(i-1) to be a random number of 8 bits length instead?



You probably want to declare "rndnum" and "easy" as arrays of

std_logic_vectors(7 downto 0) to be able to store incoming rnum values

or something. I have no idea about the algorithm, so I'm guessing here...



Besides, a std_logic or a std_logic_vector is not a numerical value,

it's a bit or a collection of bits. That's why you cannot convert it to

integer. You either have to declare the elements of your rnum1 array as

some sort of numerical value (for example unsigned(7 downto 0)) or you

have to cast before trying to convert:



int1:= to_integer(unsigned(rnum1(i-1)));



(or maybe signed, depending on what values that random number generator

delivers). The whole conversion doesn't make a whole lot of sense if

what you're converting is a single it, though.



HTH,

Sean
Click to expand...

Hey Sean, that was pretty helpful! I'll try to do the things you mentioned.
 
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