Synthesis failure Xilinx WebPack XST

Guest
Hi All,

I'm trying to synthesize the folllowing VHDL file with the Xilinx
WebPack tools. I'm synthesising for a XC3S200 chip.
When I run XST it generates one 256 bits serial register and assigns
outD and outD1 both to the same output of the shift register (I
checked with the RTL schematic viewer).
Changing outD1 <= fifo(28); to outD1 <= fifo(7); (or any other number
below 16) generates two shift registers as expected. Did I run into a
XST bug or do I something terribly wrong (I'm new to VHDL).
Version used 6.1.03i (It isn't the latest version I think but happens
to be on the PC I'm using at the moment)

Thanx,
Peter


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity test2 is
port (
clk: in std_logic;
inD: in std_logic;
outD1: out std_logic;
outD: out std_logic
);
end test2;

architecture Behavioral of test2 is
signal fifo: std_logic_vector(0 to 255);

begin
process(clk, inD)
begin
if (clk'event and clk='0') then
fifo <= fifo(1 to 255) & inD;
end if;
end process;
outD1 <= fifo(28);
outD <= fifo(0);

end Behavioral;
 
Hi All,

I'm trying to synthesize the folllowing VHDL file with the Xilinx
WebPack tools. I'm synthesising for a XC3S200 chip.
When I run XST it generates one 256 bits serial register and assigns
outD and outD1 both to the same output of the shift register (I
checked with the RTL schematic viewer).
Click to expand...
The ISE schematic viewer didn't show you everything. If you implement
the design and look at the ncd file with the FPGA editor, you will see
that outD and outD1 come from two different places.

Changing outD1 <= fifo(28); to outD1 <= fifo(7); (or any other number
below 16) generates two shift registers as expected. Did I run into a
Click to expand...
SRL16's are used for the shift registers. Two outputs cannot come from
the same SRL16 as it uses one LUT. For bit 0 and 28 case, they can be
taken from different SRL16's, so only one 256-bit shift register is
needed (16 SRL16). For bit 0 and 7 (or anything < 16) case, two shift
registers have to be used (one 249 bit and the other one 7 bit).

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips


XST bug or do I something terribly wrong (I'm new to VHDL).
Version used 6.1.03i (It isn't the latest version I think but happens
to be on the PC I'm using at the moment)

Thanx,
Peter


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity test2 is
port (
clk: in std_logic;
inD: in std_logic;
outD1: out std_logic;
outD: out std_logic
);
end test2;

architecture Behavioral of test2 is
signal fifo: std_logic_vector(0 to 255);

begin
process(clk, inD)
begin
if (clk'event and clk='0') then
fifo <= fifo(1 to 255) & inD;
end if;
end process;
outD1 <= fifo(28);
outD <= fifo(0);

end Behavioral;
Click to expand...
 
Hi,

Thanx for your reply

The ISE schematic viewer didn't show you everything. If you implement
the design and look at the ncd file with the FPGA editor, you will see
that outD and outD1 come from two different places.
Click to expand...
As far as I can see FPGA editor is not part of the WebPack tools so I
can't use that. I've tried following lines with the floorplanner, but
automatic place and route leave all SRL16 unplaced and unrouted (that
is an other mistery not yet clear to me why that happens or rather
doesn't happen). Is this a bug in the ISE schematic viewer that it
doesn't show the correct schematic? I've tried switching off the SRL16
generation and then I get the correct schematic (although with 256
seperate FF ofcourse)

Changing outD1 <= fifo(28); to outD1 <= fifo(7); (or any other number
below 16) generates two shift registers as expected. Did I run into a

SRL16's are used for the shift registers. Two outputs cannot come from
the same SRL16 as it uses one LUT. For bit 0 and 28 case, they can be
taken from different SRL16's, so only one 256-bit shift register is
needed (16 SRL16). For bit 0 and 7 (or anything < 16) case, two shift
registers have to be used (one 249 bit and the other one 7 bit).
Click to expand...
I understand that part. I will try to get both (28) and (27) to see
what the tool tries to do in that case. Because that should split the
shift register too.

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips


XST bug or do I something terribly wrong (I'm new to VHDL).
Version used 6.1.03i (It isn't the latest version I think but happens
to be on the PC I'm using at the moment)

Thanx,
Peter


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity test2 is
port (
clk: in std_logic;
inD: in std_logic;
outD1: out std_logic;
outD: out std_logic
);
end test2;

architecture Behavioral of test2 is
signal fifo: std_logic_vector(0 to 255);

begin
process(clk, inD)
begin
if (clk'event and clk='0') then
fifo <= fifo(1 to 255) & inD;
end if;
end process;
outD1 <= fifo(28);
outD <= fifo(0);

end Behavioral;
Click to expand...
 
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