Synthesis and Gate level simulation

[asic1234@gmail.com]

hi

What are the inputs and outputs for the synthesis process? What tools
are used for the same, and what file types/extensions are involved?

I am trying to learn more about the downstream process after
functionally verifying the RTL.
Ideally, I am trying to put together an excel sheet like:

Process, Input, Output, Tools used, Language/File extension used,
comments


Example would be something like:

RTL Coding (Process),
Microarchitecture spec (Input),
RTL code (.v or .vhdl files),
text editor (tools used ),
..v or .vhd (Language/File extension used)
Describes each block in verilog or vhdl (comments)

Thanks