synthese: date and time automatically placed in a register??

P

Pierre-Louis

Guest
Dear all,
is there any method to automatically put (during loading) in a register of a
synthetised FPGA a time reference,
to be able to verify later the running version (by JTAG, for example) ?

At this time, I write manually a 16 bits "reference" constant in a package,
and I set a dedicated register to this value during global reset of the
FPGA.
That works, if I don't forget to modify the constant before each
compilation!

Thanks in advance,
Pierre-Louis
 
"Pierre-Louis" <otemoi.pierrelouis.liotard@free.fr> wrote in
message news:bmj4go$f22$1@ccpntc8.in2p3.fr...

is there any method to automatically put (during loading) in a register of
a
synthetised FPGA a time reference,
to be able to verify later the running version (by JTAG, for example) ?
Click to expand...
I don't know any way to hack this sort of thing into the bit stream,
unless you can do it by setting some ROM initialisation value. Try
asking on comp.arch.fpga where the FPGA implementation gurus live.

However, I *do* know how to do it at the synthesis stage, without
interfering with your VHDL source code.

If your synthesis tool has a Tcl scripting shell (true for Synplify,
Leonardo, Precision, Synopsys DC and probably many others) then you
can do it from the synthesis script. Set up an integer generic in
your top-level design, and use that generic to construct your date tag
within the logic. Configure that generic from your script at elaboration.
Tcl can easily construct an integer based on the date and time. This
little Tcl proc constructs an integer whose value is the number of hours
since midnight on the 1st Jan 2000, displays it in both decimal and hex,
and returns the value so that you can use it elsewhere in the script:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
proc hours_since_millennium {} {
set now [clock seconds]
set millennium [clock scan 01-jan-2000]
set diff [expr {($now - $millennium) / 3600}]
puts "Hours since millennium: $diff = [format 0x%04X $diff]"
return $diff
}
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Suppose your top-level VHDL is just this...

~~~~~~~~~~~ file: date.vhd ~~~~~~~~~~~~~~~~~~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity has_ID is
generic (ID_value: natural := 0);
port (ID: out std_logic_vector(15 downto 0));
end;

architecture rtl of has_ID is
begin
ID <= std_logic_vector(to_unsigned(ID_value, ID'length));
end;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

A suitable synthesis script for Leo Spectrum looks something
like this... other tools will be broadly similar.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# Read without elaboration, so we can set the generic later
read -technology "xis2" -dont_elaborate
C:/jseb/oddments/vhdl/Fun/date.vhd }
# Now elaborate the top-level, with appropriate setting for the generic
elaborate has_ID -architecture rtl -generics
ID_value=[hours_since_millennium]
# Finally, do your pre-optimize and optimize steps as usual.
....
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Thank you a lot, Jonathan.
I'll try your method that I sum up:
get the time tag with a tcl script, and launch the synthesis of the top
level in the tcl script, with the tag as a generic.
At this time, I don't use any tcl script with Synplify. I have to learn
that.
Pierre-Louis
 
Help! I don't find how to pass any generic with Synplify with the tcl script
"project -run compile " command...
Pierre-Louis
 
If you use Xilinx FPGA you can use bitgen to set the JTAG-ID.
Try bitgen -g USER_ID = 0x00000000 ... and
bitgen -h for more information

In the 6.1i manual only Spartan-3 is mentioned, this works at least for
Virtex-E as well.

Chris



Pierre-Louis wrote:

Dear all,
is there any method to automatically put (during loading) in a register of a
synthetised FPGA a time reference,
to be able to verify later the running version (by JTAG, for example) ?

At this time, I write manually a 16 bits "reference" constant in a package,
and I set a dedicated register to this value during global reset of the
FPGA.
That works, if I don't forget to modify the constant before each
compilation!

Thanks in advance,
Pierre-Louis
Click to expand...
 
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bmj983$g35$1$830fa17d@news.demon.co.uk>...
If your synthesis tool has a Tcl scripting shell (true for Synplify,
Leonardo, Precision, Synopsys DC and probably many others) then you
can do it from the synthesis script. Set up an integer generic in
Click to expand...
Setting the values of top-level generics at sythesis works if you are
using Leonardo or the latest version of synplify. This does not work
with precision and I don't know about synopsys dc.
 
"Chrisitian Schneider" <cgs-news@cgschneider.com> wrote in
message news:bmk663$p3l$1@online.de...
If you use Xilinx FPGA you can use bitgen to set the JTAG-ID.
Try bitgen -g USER_ID = 0x00000000 ... and
bitgen -h for more information
Click to expand...
Thanks. But how do you get at this user-id "at runtime"
(i.e. from within the FPGA fabric) rather than from the
JTAG scan chain?
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Pierre,

If you are using Synplify Pro there is a Tcl script available
to automatically update a VHDL Package with the current date, time
and eventually (Work in-progress) a CVS tag rev number when the Run
button is pushed.

Please let me know if you are interested and I can send you the script.

Thank You,

Bob

Synplicity FAE Colorado/Utah

Pierre-Louis wrote:
Dear all,
is there any method to automatically put (during loading) in a register of a
synthetised FPGA a time reference,
to be able to verify later the running version (by JTAG, for example) ?

At this time, I write manually a 16 bits "reference" constant in a package,
and I set a dedicated register to this value during global reset of the
FPGA.
That works, if I don't forget to modify the constant before each
compilation!

Thanks in advance,
Pierre-Louis
Click to expand...



 
However, I *do* know how to do it at the synthesis stage, without
interfering with your VHDL source code.
Click to expand...
Using a top-level Generic (or Parameter) to pass a date
time value into the code is very elegant and has some definite
advantages for porting code between synthesis/simulation tools.

The script some customers are using for Synplify/Amplify,
uses tcl to automatically create a VHDL package (or Verilog Include)
file which is accessed within the design. The script has been in use
by some for about a year.

Based on some customer experiences, the biggest warning on using
a "dynamic" constant in your design is to make sure that the constant
is registered or placed in a ROM in your code. I've seen two cases
where the TIME value was not registered and was used to drive a large
critical path MUX. Synthesis would optimize this MUX better or worse
depending on the "time of day" causing the design to make timing some
days and not others. Please don't torture your local Synplicity,
Xilinx, or Altera FAEs and yourself with a problem like this :) by
making sure the time or date value is registered. Many synthesis tools
also optimize out registers driven by constants so you may need
a syn_preserve directive on the register.


Thank You,

Bob
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top