Syntax question: using WHEN statement

L

lomtik

Guest
Hi, how do I implement something like that in one line, so that I
don't drive DOUT at two locations?

DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');

Thanks
 
lomtik wrote:


DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');
Click to expand...

DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='1') else
DO_lower(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='0');


Note: This will result in a latch.

Ralf
 
use case statement or use a multiplexer with do_higher and d0_lower as its
input and dout as the output, then use addr(8) as the select line, but
this requires remodelling your design upto the rtl level.
 
rickman wrote:


DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');


DOUT <= '0' when not (CSN='0' and RDN='0') else
DO_higher(SAMPLE_WIDTH-1 downto 0) when ADDR(8)='1' else
DO_lower(SAMPLE_WIDTH-1 downto 0);

Note: This will NOT result in a latch.
Click to expand...
ACK - this is not a latch - but this is not exactly the same as in the
original idea. The OP should use a similar solution to yours depending
on the context.

Ralf
 
Continuing with your methodology, you could write:
DOUT1 <= DO_higher(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='1')
else (others => '0') ;
DOUT2 <= DO_lower(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='0')
else (others => '0') ;

DOUT <= DOUT1 or DOUT2 ;
Click to expand...
Using above, DOUT1 and DOUT2 are (SAMPLE_WIDTH-1 downto 0) vectors.
What will be "DOUT <= DOUT1 or DOUT2" then (one of these vectors or
'1' for all cases but the one when both of them are 0-vectors)?

Thanks
 
lomtik,
You probably want to start a new thread for a new question.

Latches only happen in non-clocked based processes. So
there is no concern in the process below.

The basic rule for latch creation in a combinational logic process:
If a signal is assigned a value for an execution of a
process, then a latch will be created if there exists
a hardware execution of the process for which the
signal does not get a value.

An example of non-hardware execution of a process would be evaluating
an 'X' condition.

Cheers,
Jim

What are the rules compiler is following when deciding whether to
generate a latch or not? As far as I see it depends on the last else
statement with DEFAULT_VALUE like zero vector.


However, today I came across another similar question regarding a latch
produced inside a process.
What should I do to avoid the latch below? I don't want any delays when
resetting max_sample and min_sample in a sequential design. In other
words, I would like to keep track of the maximum value over one
sample_clk period (max_sample should contain maximum value at the last
CLK of the period).

process(CLK)
begin
if (clk'event and clk='1') then
if (sample_clk_edge='1') then
-- Reset each sample clock
max_sample <= (others => '0');
min_sample <= (others => '0');
end if;
if signed(SAMPLE_IN) > signed(max_sample)) then
max_sample <= SAMPLE_IN;
end if;
end if;
end process;
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Ralf Hildebrandt wrote:
lomtik wrote:

DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');
Click to expand...
DOUT <= '0' when not (CSN='0' and RDN='0') else
DO_higher(SAMPLE_WIDTH-1 downto 0) when ADDR(8)='1' else
DO_lower(SAMPLE_WIDTH-1 downto 0);

Note: This will NOT result in a latch.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
lomtik wrote:
Hi, how do I implement something like that in one line, so that I
don't drive DOUT at two locations?

DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0'
and ADDR(8)='0');
Click to expand...
Continuing with your methodology, you could write:
DOUT1 <= DO_higher(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='1')
else (others => '0') ;
DOUT2 <= DO_lower(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='0')
else (others => '0') ;

DOUT <= DOUT1 or DOUT2 ;

Otherwise, in general "when/if" for independent datapaths leads
to priority select logic (which can be slower and smaller). Note
though that priority select logic with up to 3 inputs, is
usually ok.

In VHDL-200X we are overloading "AND" to give you a simple solution
to this problem:

DOUT <=
(DO_higher(SAMPLE_WIDTH-1 downto 0) and (not CSN and not RDN and Addr(8)) or
( DO_lower(SAMPLE_WIDTH-1 downto 0) and (not CSN and not RDN and not Addr(8)) ;

-- of course if you like this, you could borrow the function from the
-- proposed ieee package and temporarily put it in yours.


For now, most of the time I prefer using case to solve this issue
as shown below. I particularly like getting the 'X' when Addr = 'X'

process(CSN, RDN, Addr, DO_higher, DO_lower)
begin
if (not CSN and not RDN) = '1' then
case Addr is
when '0' => DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) ;
when '1' => DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) ;
when others => DOUT <= (others => 'X') ; -- All X's
end case ;
else
DOUT <= (others => '0') ; -- All 0's
end if ;
end process ;

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
What are the rules compiler is following when deciding whether to
generate a latch or not? As far as I see it depends on the last else
statement with DEFAULT_VALUE like zero vector.


However, today I came across another similar question regarding a latch
produced inside a process.
What should I do to avoid the latch below? I don't want any delays when
resetting max_sample and min_sample in a sequential design. In other
words, I would like to keep track of the maximum value over one
sample_clk period (max_sample should contain maximum value at the last
CLK of the period).

process(CLK)
begin
if (clk'event and clk='1') then
if (sample_clk_edge='1') then
-- Reset each sample clock
max_sample <= (others => '0');
min_sample <= (others => '0');
end if;
if signed(SAMPLE_IN) > signed(max_sample)) then
max_sample <= SAMPLE_IN;
end if;
end if;
end process;
 
lomtik wrote:

Continuing with your methodology, you could write:
DOUT1 <= DO_higher(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='1')
else (others => '0') ;
DOUT2 <= DO_lower(SAMPLE_WIDTH-1 downto 0)
when (CSN='0' and RDN='0' and ADDR(8)='0')
else (others => '0') ;

DOUT <= DOUT1 or DOUT2 ;


Using above, DOUT1 and DOUT2 are (SAMPLE_WIDTH-1 downto 0) vectors.
What will be "DOUT <= DOUT1 or DOUT2" then (one of these vectors or
'1' for all cases but the one when both of them are 0-vectors)?

When DOUT1 or DOUT2 are not selected, their value will be
Click to expand...
all '0'. Since only one can be selected at a time, DOUT
will either have the value from DO_Higher (if DOUT1 is selected),
DO_Lower (if DOUT2 is selected) or all '0' if neither is
selected.

Hence, what you have created is and-or logic.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
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