Syntax Problem

[Dave Wilson]

Hello all,

I'm trying to convert some VHDL code to Verilog and have a few syntax
problems. Can anyone see what I'm doing wrong in this code ?

// 18-06-04

module sync_compare_verilog(clk,aclr,enable,out,get_ready_pulse
,main_sync,sync_polarity,missing_sync,sync_valid,sync_out);

input clk,aclr,enable,get_ready_pulse,main_sync,sync_polarity,missing_sync;

output sync_valid,sync_out;

reg sync_valid;
reg sync_out;
reg state;

parameter zero=0, one=1;

always @(state)
begin
case (state)
zero:
out = 1'b0;
one:
out = 1'b1;
default:
out = 1'b0;
endcase
end

always @(posedge clk or posedge aclr)
begin
if (aclr)

sync_valid = 1'b0;
sync_out = 1'b0;
state = zero;
else
case (state)
zero: // ----------------------------- STATE 0

if (enable == 1'b1) // wait for enable
if (get_ready_pulse == 1'b1)
if (main_sync == 1'b1) and (sync_polarity = 1'b0) // check which
way ..
sync_valid = 1'b1;
// sync_out = main_sync; -- = 1
state = one;
else if (main_sync == 1'b0) and (sync_polarity == 1'b1)
sync_valid = 1'b1;
// sync_out = main_sync; -- = '0'
state = one;
else
sync_valid = 1'b0;
// sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
sync_valid = 1'b0;
//sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
state = zero;
end;

one: // ---------------------------------------- STATE 1

if (missing_sync == 1'b1)
sync_valid = 1'b0;
state = zero;
else
state = one;
//sync_out = main_sync;
end;
endcase
end;
endmodule

 

[Andy Peters]

da_wils@hotmail.com (Dave Wilson) wrote in message news:<6895fdb2.0406180241.5bb1f918@posting.google.com>...

Hello all,

I'm trying to convert some VHDL code to Verilog and have a few syntax
problems. Can anyone see what I'm doing wrong in this code ?

You should post the error messages and tell us what tools you're
using.

// 18-06-04

module sync_compare_verilog(clk,aclr,enable,out,get_ready_pulse
,main_sync,sync_polarity,missing_sync,sync_valid,sync_out);

input clk,aclr,enable,get_ready_pulse,main_sync,sync_polarity,missing_sync;

output sync_valid,sync_out;

Well, for style reasons, you should list each signal on its own line,
perhaps with a comment indicating the signal's use. Otherwise, your
code is basically unreadable.

reg sync_valid;
reg sync_out;
reg state;

parameter zero=0, one=1;

always @(state)

You've declared a single-bit state register, yet you declare your
state parameters as integers. Save yourself some aggravation by
making the state parameters the same size as the state register.

begin
case (state)
zero:
out = 1'b0;
one:
out = 1'b1;
default:
out = 1'b0;
endcase
end

I don't understand why you did that, but ...

always @(posedge clk or posedge aclr)

[snip]

end;

Don't put a semicolon after end.

else
sync_valid = 1'b0;
//sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;

Here too. And elsewhere.

-a

 

[Gabor Szakacs]

You need begin .. end whenever multiple statements fall within
the if or else clause:

da_wils@hotmail.com (Dave Wilson) wrote in message news:<6895fdb2.0406180241.5bb1f918@posting.google.com>...

Hello all,

I'm trying to convert some VHDL code to Verilog and have a few syntax
problems. Can anyone see what I'm doing wrong in this code ?

// 18-06-04

module sync_compare_verilog(clk,aclr,enable,out,get_ready_pulse
,main_sync,sync_polarity,missing_sync,sync_valid,sync_out);

input clk,aclr,enable,get_ready_pulse,main_sync,sync_polarity,missing_sync;

output sync_valid,sync_out;

reg sync_valid;
reg sync_out;
reg state;

parameter zero=0, one=1;

always @(state)
begin
case (state)
zero:
out = 1'b0;
one:
out = 1'b1;
default:
out = 1'b0;
endcase
end

always @(posedge clk or posedge aclr)
begin
if (aclr)
begin

sync_valid = 1'b0;
sync_out = 1'b0;
state = zero;
end
else
case (state)
zero: // ----------------------------- STATE 0

if (enable == 1'b1) // wait for enable
if (get_ready_pulse == 1'b1)
if (main_sync == 1'b1) and (sync_polarity = 1'b0) // check which
way ..
begin
sync_valid = 1'b1;
// sync_out = main_sync; -- = 1
state = one;
end
else if (main_sync == 1'b0) and (sync_polarity == 1'b1)
begin
sync_valid = 1'b1;
// sync_out = main_sync; -- = '0'
state = one;
end
else
begin
sync_valid = 1'b0;
// sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end
end;
else
begin
sync_valid = 1'b0;
//sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end
end;
else
state = zero;
end;

one: // ---------------------------------------- STATE 1

if (missing_sync == 1'b1)
begin
sync_valid = 1'b0;
state = zero;
end
else
state = one;
//sync_out = main_sync;
end;
endcase
end;
endmodule