Syntax for Always with neg/pos edge AND logic level (i.e.

[benn]

I'd like to latch a whats on the data bus when the Write signal goes
low, and the chip select is low...

However, since CS goes low before WR they do not occur at the same
time. How can I specify in the always block to trigger off of WR
going low and that CS also must also be low.

From what I've read, doing something like:
always @(negedge wr and cs)

will trigger whenever cs changes (posedge or negedge).. not exactly
what I'm looking for!

 

[Jason Zheng]

What you are looking for is:

always @ (wr or cs)
if (wr===1'b0 && cs===1'b0)
dosomething;

Keep in mind this will not synthesize. Another way to write it:

initial forever
begin
wait (wr===1'b0 && cs===1'b0);
dosomthing;
wait (wr!==1'b0 || cs!==1'b0);
end

On Tue, 3 Jun 2008 16:43:45 -0700 (PDT)
benn <benn686@hotmail.com> wrote:

I'd like to latch a whats on the data bus when the Write signal goes
low, and the chip select is low...

However, since CS goes low before WR they do not occur at the same
time. How can I specify in the always block to trigger off of WR
going low and that CS also must also be low.

From what I've read, doing something like:
always @(negedge wr and cs)

will trigger whenever cs changes (posedge or negedge).. not exactly
what I'm looking for!

--
My friend has a baby. I'm writing down all the noises he makes so
later I can ask him what he meant.
-- Steven Wright

 

[John_H]

benn wrote:

I'd like to latch a whats on the data bus when the Write signal goes
low, and the chip select is low...

However, since CS goes low before WR they do not occur at the same
time. How can I specify in the always block to trigger off of WR
going low and that CS also must also be low.

From what I've read, doing something like:
always @(negedge wr and cs)

will trigger whenever cs changes (posedge or negedge).. not exactly
what I'm looking for!

How about
always @(negedge wr)
if( cs ) begin
...
end

 

[bigcaterpillar@gmail.com]

synchronous or aynochronous cs?

 

[Chris F Clark]

John_H <newsgroup@johnhandwork.com> writes:

benn wrote:
I'd like to latch a whats on the data bus when the Write signal goes
low, and the chip select is low...
....
How about
always @(negedge wr)
if( !cs ) begin
^
...
end

I second this one, with the very slight modification shown. It says,
when the following event occurs (negedge write), check to see (at that
instant) that the chip select signal is (alreay) low, and if so,
execute the code in the block, represented by the elipsis (...).

 

[John_H]

benn wrote:

I'd like to latch a whats on the data bus when the Write signal goes
low, and the chip select is low...

However, since CS goes low before WR they do not occur at the same
time. How can I specify in the always block to trigger off of WR
going low and that CS also must also be low.

From what I've read, doing something like:
always @(negedge wr and cs)

will trigger whenever cs changes (posedge or negedge).. not exactly
what I'm looking for!

Chris caught something I just glossed over; active low signals can get
rather confusing especially to other designers working with your
code. Ways to avoid the confusion include indicating the signals are
negated logic through naming - using something like nCS or WR_n - or
just converting your signals from inverted to normal logic at the top
level file:

input nCS;
wire CS = ~nCS;

While neither of these will affect the actual logic when you implement
with the correct polarities, it makes support simpler.

- John