synplify+Logic does not match a flip-flop

[srini]

Hi,
I am using Synplify Pro for the first time. When I run my project, I am
getting the following error: "The logic for am_niose_count[31:0] does
not match a standard flip-flop". I have declared am_noise_count as an
integer.
Can anyone help to solve this problem?

 

[gabor]

srini wrote:

Hi,
I am using Synplify Pro for the first time. When I run my project, I am
getting the following error: "The logic for am_niose_count[31:0] does
not match a standard flip-flop". I have declared am_noise_count as an
integer.
Can anyone help to solve this problem?

You would need to show more of your code. It is not likely that the
integer declaration is causing the problem. More likely the process
code (always @ ...) is written in such a way that a flip-flop cannot be
inferred. Things that can cause this are use of both clock edges,
use of more than one clock signal, assignments in more than one
process block...

The standard process block for inferring a flip-flop with an
asynchronous
preset or clear looks like:

reg flop;
always @ (posedge clock or posedge clear)
if (clear) flop <= 0;
else flop <= d_function;

Normally you'd use begin / end blocks and have more than one
statement for each condition of the "if (clear)".

One common mistake that can cause a flip-flop to become non-
synthesizable is to use "posedge clear" in the dependencies list
and then "if (something_else)" for the reset term. This would
represent
a flip-flop with more than one clock function. Perfectly useable for
simulation, but not available in silicon.

Hope this helps,
Gabor