M
MM
Guest
The code below compiles fine in Active HDL and synthesizes by XST, however
Synplify says
that the sig_num((sig_num'Left - 1) downto 0) slice is out of range. How
should I write it so it will understand?
/Mikhail
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
package num_convert is
function two_cmplt ( sig_num : std_logic_vector )
return std_logic_vector;
end package num_convert ;
package body num_convert is
function two_cmplt ( sig_num : std_logic_vector )
return std_logic_vector is
variable result : std_logic_vector (sig_num'LENGTH-1 downto 0);
begin
if sig_num(sig_num'Left)='1' then
result := '1' & ((not sig_num((sig_num'Left - 1) downto 0)) + 1);
else
result := sig_num;
end if;
return result;
end two_cmplt;
end package body num_convert;
---------------------------------------------------------------------------
Synplify says
that the sig_num((sig_num'Left - 1) downto 0) slice is out of range. How
should I write it so it will understand?
/Mikhail
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
package num_convert is
function two_cmplt ( sig_num : std_logic_vector )
return std_logic_vector;
end package num_convert ;
package body num_convert is
function two_cmplt ( sig_num : std_logic_vector )
return std_logic_vector is
variable result : std_logic_vector (sig_num'LENGTH-1 downto 0);
begin
if sig_num(sig_num'Left)='1' then
result := '1' & ((not sig_num((sig_num'Left - 1) downto 0)) + 1);
else
result := sig_num;
end if;
return result;
end two_cmplt;
end package body num_convert;
---------------------------------------------------------------------------