Synplicity Synthesis of VHDL module

[salman sheikh]

I am trying to synthesize a floating point multiplier that uses a
generate state to create an adder tree. I simulated it fine, but
synthesis complains about a problem that I can't seem to get past.

I am using Synplify Pro 7.3.3 and my log file looks like this:

Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
.....
....
Synthesizing fplib.fpmul_addtree_clk.arch
Synthesizing fplib.fpmul_addtree_clk.arch
@E:"C:\FPLibrary-0.91\vhdl_fponly\fp\pkg_fpmul\fpmul_addtree_clk.vhd":75:41:75:51|*
with negative exponent -1
@E:"C:\FPLibrary-0.91\vhdl_fponly\fp\pkg_fpmul\fpmul_addtree_clk.vhd":101:39:101:49|*
with negative exponent -1
Synthesizing fplib.fpmul_addtree_clk.arch
2 errors during synthesis
@END

The fpmul_addtree_clk was not written by me. It uses a generate
statement to instantiate itself a certain number of times. I think it is
going down to the point where it is getting a negative number for one of
the generics. How can I stop this, if this is the problem?

Thanks in advance.

Salman