D
Davy
Guest
Hi all,
I want to use SystemVerilog to construct next generation of my
testbench.
And I found Synopsys provide VMM while Mentor provide AVM. Anyone can
give some comment on these two methodology? Or are they similar?
I don't know if Synopsys's VMM is open document and open source code.
The AVM cookbook/source code, you can download a free copy from:
http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm
Best regards,
Davy
I want to use SystemVerilog to construct next generation of my
testbench.
And I found Synopsys provide VMM while Mentor provide AVM. Anyone can
give some comment on these two methodology? Or are they similar?
I don't know if Synopsys's VMM is open document and open source code.
The AVM cookbook/source code, you can download a free copy from:
http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm
Best regards,
Davy