synopsys library to xilinx

[sundar]

hi all,
i am in the process of porting asic to fpga.
during this process i found my existing asic is using synopsys
library. but my target fpga is in xilinx.
i dont have synopsys license and related libraries and hence my ise
tool doesnt recognize synopsys libs.
help me to port synopsys to xilinx libs.

rgs,
sundar

 

[Mike Treseler]

sundar wrote:

hi all,
i am in the process of porting asic to fpga.
during this process i found my existing asic is using synopsys
library. but my target fpga is in xilinx.
i dont have synopsys license and related libraries and hence my ise
tool doesnt recognize synopsys libs.
help me to port synopsys to xilinx libs.

Your choices are:
1. Rewrite your code using generic rtl.
2. Rewrite your code using brand X templates or cores.
3. Buy a synopsys license to port the old code to xilinx,
if this exists. Chances are, some changes will be needed anyway.

Make sure you have a working testbench first.

-- Mike Treseler

 

[Jonathan Bromley]

On Tue, 18 Nov 2008 01:35:21 -0800 (PST), sundar wrote:

i am in the process of porting asic to fpga.
during this process i found my existing asic is using synopsys
library. but my target fpga is in xilinx.
i dont have synopsys license and related libraries and hence my ise
tool doesnt recognize synopsys libs.
help me to port synopsys to xilinx libs.

Given the constraints you describe, Mike Treseler is
pretty much correct. For sure there is no escape
from spending either money or time; which do you
have in greater supply?

I believe that the full-spec versions of Synplify
know quite a lot about Synopsys primitives and how
to map them to FPGA elements. Now that Synopsys has
acquired Synplicity, this is even more likely to be
your preferred path.

Other high-end FPGA synthesis tools may have similar
features; I've not explored this in depth. These
full-featured FPGA synth tools are often used in
projects where ASICs are prototyped on FPGA, so
the problems you describe have been met and at
least partially solved many times before.

Beware of ASIC primitives that have no useful
equivalent in FPGA: the obvious problem areas
are latch-based or asynchronous designs,
functions based on pass-transistor logic, and
anything analogue such as crystal oscillators,
A/D and D/A, PHYs for interfaces like USB,
and so on. Power-down circuitry can be hard
to map across, too.

Good luck.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[sundar]

On Nov 18, 9:41 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Tue, 18 Nov 2008 01:35:21 -0800 (PST), sundar wrote:
i am in the process of porting asic to fpga.
during this process i found my existing asic is using synopsys
library. but my target fpga is in xilinx.
i dont have synopsys license and related libraries and hence my ise
tool doesnt recognize synopsys libs.
help me to port synopsys to xilinx libs.

Given the constraints you describe, Mike Treseler is
pretty much correct.  For sure there is no escape
from spending either money or time; which do you
have in greater supply?

I believe that the full-spec versions of Synplify
know quite a lot about Synopsys primitives and how
to map them to FPGA elements.  Now that Synopsys has
acquired Synplicity, this is even more likely to be
your preferred path.

Other high-end FPGA synthesis tools may have similar
features; I've not explored this in depth.  These
full-featured FPGA synth tools are often used in
projects where ASICs are prototyped on FPGA, so
the problems you describe have been met and at
least partially solved many times before.

Beware of ASIC primitives that have no useful
equivalent in FPGA: the obvious problem areas
are latch-based or asynchronous designs,
functions based on pass-transistor logic, and
anything analogue such as crystal oscillators,
A/D and D/A, PHYs for interfaces like USB,
and so on.  Power-down circuitry can be hard
to map across, too.

Good luck.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks Jonathan and Mike

As you have mentioned options....
1) I may not be purchasing Synopsys tool...even in that case I doubt
like Jonathan mentioned about ASIC equivalents in FPGA
2) other idea like you have mentioned is to go for synplify. this may
happen. i still doubt if a synplify premier with DP could recognize
most of synopsys attributes.
3) 3rd option is to identify/analyze and create equivalent xilixn
unisim primitives...
this is my understanding....pls add your thots

Thanks and Regards,
sundar

 

[Mike Treseler]

sundar wrote:

3) 3rd option is to identify/analyze and create equivalent xilixn
unisim primitives...

With plain rtl code, ISE will infer primitives ok.
Device specific structures like ram
may require a code template or a library instance.

-- Mike Treseler