syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVID

[John Providenza]

If I have a 500MHz input clock feeding into two DCMs in a Virtex-II
with the CLKIN_DIVIDE_BY_2 option set on both of them....

The CLK0 output of each of them should be 250MHz, but it seems
like they could come up 180 degrees out of phase.

Is there any way to have the CLK0 outputs of the two DCMs
come up "in phase" without playing tricks with the CLKFB
signals between the two of them?



Thanks

John Providenza

 

[Austin Lesea]

John,

There is no way to synchronize two separate DCM CLKDV outputs in phase,
nor is there a way to synchronize the CLKDV with the CLKFX phase (where
they are both say dividing by 1/2) that we are aware of.

This is a deficiency that we realized, and are planning to fix in
subsequent generations.

The logic that generates the sequence has no ability to be reset or
strobed by a user logic signal to cause them to be in sync.

Just to help us, why do you do the same thing twice? If you explain
what you are doing, perhaps there is another way to do it?

Austin


John Providenza wrote:

If I have a 500MHz input clock feeding into two DCMs in a Virtex-II
with the CLKIN_DIVIDE_BY_2 option set on both of them....

The CLK0 output of each of them should be 250MHz, but it seems
like they could come up 180 degrees out of phase.

Is there any way to have the CLK0 outputs of the two DCMs
come up "in phase" without playing tricks with the CLKFB
signals between the two of them?

Thanks

John Providenza

 

[John Providenza]

Austin -

I'm trying to generate three phase adjustable clocks, although my example
only talks about 2 DCMs for two clocks.

The current design uses one variable phase shift DCM to divide down
the input 500MHz (using CLKIN_DIVIDE_BY_2) into a phase adjustable 250MHz.
Incoming data is coming in sync'd to the 500MHz clock, so this phase
adjustment lets me tweak the stup/hold time for the incoming data.

In the current design, 2 other DCMs are cascaded off the "primary" DCM
to allow us to create 2 phase adjustable clocks. No clock manipulation,
just CLKIN leading to CLK0 and CLK180. We need to adjust these two
phases independently, thus 2 DCMs for these.

Our timing margins are tight, and I'd like to avoid cascading the
jitter from the primary DCM into the 2 secondary DCMs.

I find little information about how the CLKIN_DIVIDE_BY_2 option
effects timing, etc, so any insight is appreciated.

Thanks for your help.

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8480BA.4ACBFDD@xilinx.com>...

John,

There is no way to synchronize two separate DCM CLKDV outputs in phase,
nor is there a way to synchronize the CLKDV with the CLKFX phase (where
they are both say dividing by 1/2) that we are aware of.

This is a deficiency that we realized, and are planning to fix in
subsequent generations.

The logic that generates the sequence has no ability to be reset or
strobed by a user logic signal to cause them to be in sync.

Just to help us, why do you do the same thing twice? If you explain
what you are doing, perhaps there is another way to do it?

Austin


John Providenza wrote:

If I have a 500MHz input clock feeding into two DCMs in a Virtex-II
with the CLKIN_DIVIDE_BY_2 option set on both of them....

The CLK0 output of each of them should be 250MHz, but it seems
like they could come up 180 degrees out of phase.

Is there any way to have the CLK0 outputs of the two DCMs
come up "in phase" without playing tricks with the CLKFB
signals between the two of them?

Thanks

John Providenza

 

[Austin Lesea]

John,

OK, got it.

The CLKIN_DIVIDE_BY_2 is a simple high speed toggle flip flop at the input of the DCM with a
dummy FF of identical delay in the clock FB path (to allow for proper phase alignement).

This FF has no ability to be synchronized (reset).

I agree that you do not want to cascade DCMs as the p-p jitter does accumulate as the square root
of the sum of the squares which takes away timing margin.

It is possible to multiplex two clocks by passing them to a BUFGMUX element, so taking the CLK0
and CLK180 to the BUFGNUX would allow selection of the "right" clock. You would have to take the
CLKFB from the CLK2X back to the CLKIN, however (as if you make the CLK180 the feedback, it would
then make CLK180 = CLK0!!!).

Resetting the DCM repeatedly until you get the phase you want is also problematical, as it may
take many resets to accidentally get the "right" phase alignment from two separate DCMs.

Is it possible to change the design so that all you use is the phase shifted version of the
clocks? The shifted CLK180 used instead of the non-shifted CLK0?

Austin

John Providenza wrote:

Austin -

I'm trying to generate three phase adjustable clocks, although my example
only talks about 2 DCMs for two clocks.

The current design uses one variable phase shift DCM to divide down
the input 500MHz (using CLKIN_DIVIDE_BY_2) into a phase adjustable 250MHz.
Incoming data is coming in sync'd to the 500MHz clock, so this phase
adjustment lets me tweak the stup/hold time for the incoming data.

In the current design, 2 other DCMs are cascaded off the "primary" DCM
to allow us to create 2 phase adjustable clocks. No clock manipulation,
just CLKIN leading to CLK0 and CLK180. We need to adjust these two
phases independently, thus 2 DCMs for these.

Our timing margins are tight, and I'd like to avoid cascading the
jitter from the primary DCM into the 2 secondary DCMs.

I find little information about how the CLKIN_DIVIDE_BY_2 option
effects timing, etc, so any insight is appreciated.

Thanks for your help.

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8480BA.4ACBFDD@xilinx.com>...
John,

There is no way to synchronize two separate DCM CLKDV outputs in phase,
nor is there a way to synchronize the CLKDV with the CLKFX phase (where
they are both say dividing by 1/2) that we are aware of.

This is a deficiency that we realized, and are planning to fix in
subsequent generations.

The logic that generates the sequence has no ability to be reset or
strobed by a user logic signal to cause them to be in sync.

Just to help us, why do you do the same thing twice? If you explain
what you are doing, perhaps there is another way to do it?

Austin


John Providenza wrote:

If I have a 500MHz input clock feeding into two DCMs in a Virtex-II
with the CLKIN_DIVIDE_BY_2 option set on both of them....

The CLK0 output of each of them should be 250MHz, but it seems
like they could come up 180 degrees out of phase.

Is there any way to have the CLK0 outputs of the two DCMs
come up "in phase" without playing tricks with the CLKFB
signals between the two of them?

Thanks

John Providenza