Synchronous processes and delays

[Thomas]

let's assume 2 entities:

a, with input_a and output_a as signals
b, with input_b and output_b as signals

now, let's assume in my design, both processes are synchronous but output_a
is connected to input_b;
if the propagation time is high between input_a and output_a, what happens?

- process b is run only when input_b's ready?

or

- when the clock ticks, process b takes whatever's in input_b, meaning it
will run one tick after process a?


in practice, the case I have is a bus decoding that is doing a bunch of
operations and then creating chipselect signals to the various parts of the
design, but these have to run on the same clock tick as well

 

[Thomas]

so, this means if I decode the address during rising phi2, I can't really
do anything synchronous, requiring the use of the decoded information, at
the same time, I have to keep all the operations for the falling edge
(right before hold time), is that right?


On Sun, 06 Jul 2003 11:05:08 +0200, Mario Trams <mtr@informatik.tu-
chemnitz.de> wrote:

Thomas wrote:

let's assume 2 entities:

a, with input_a and output_a as signals
b, with input_b and output_b as signals

now, let's assume in my design, both processes are synchronous but
output_a is connected to input_b;
if the propagation time is high between input_a and output_a, what
happens?

- process b is run only when input_b's ready?

In VHDL, a signal is never "ready" - it is just there and might change at
any time.

or

- when the clock ticks, process b takes whatever's in input_b, meaning
it
will run one tick after process a?

Yes, that is the case. output_b will be delayed by one cycle compared to
output_a.

in practice, the case I have is a bus decoding that is doing a bunch of
operations and then creating chipselect signals to the various parts of
the design, but these have to run on the same clock tick as well

As I know that you are working on a 6502-Bus:
If you need a synchronous decoding, you should register the address
(or even the decoded signals) at the rising edge of Phi2. This gives you
a clean timing as all data transfers happen at the falling edge of Phi2.

Regards,
Mario

 

[Mario Trams]

Thomas wrote:

so, this means if I decode the address during rising phi2, I can't really

Better say: "register the decoding result at rising Phi2"

do anything synchronous, requiring the use of the decoded information, at
the same time, I have to keep all the operations for the falling edge
(right before hold time), is that right?

Basically Yes. The first opportunity to evaluate the signals
registered at the rising Phi2 is at the falling Phi2.
(Btw.: That's the nature of the 6502 architecture. It is pipelined
like a master-slave flip flop.)

Note that a registered (synchronous) address decoding on the 6502
bus is not necessarily required.

If you need to do some clocked operations in between rising and falling
clock edges, you should consider using a higher clock for your logic
(say 2 times CPU-clock).

Regards,
Mario



--
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Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
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