Synchronizing Reset De-assertion

[Satya]

Hi,
This may be a basic question. I have read that 'reset' should not be
de-asserted asynchronously. To de-assert this synchronously, is there
any special circuit needed.

I have come across a ciruit, where in it is given that use the
synchronizer without reset to synchronize the reset going to main
design. Also use as many synchronizers equal to the clock domains in
the design. But my doubt is, what is it meant by synchronizer without
reset, will the reset be tied to high for these flip-flops. Also, is
there any difference in ASIC and FPGA environments in Synchronizing
the reset.

Thanks and regards,

Satya

 

[Mike Treseler]

Satya wrote:

Hi,
This may be a basic question. I have read that 'reset' should not be
de-asserted asynchronously. To de-assert this synchronously, is there
any special circuit needed.

There might be a cpu on your board.
Run the fpga on the cpu clock.
At boot time, have the cpu load the fpga
then provide the reset pulse.

-- Mike Treseler