Synchronizer doubts

Hi folks,

I have a basic doubt in digital design, Suppose if I have a 20mhz clock
domain A and say a 50Mhz another clock domain B,Clock domain B sents an
interupt to domain A which operates of 20Mhz, How should i synchonize
this signal to acknowledge the interupt ?

If asynchrnous , then we can use hand shake signal ? but how it wil b
in synchrnous system ?

Can i use a fifo and give clk A as reference clk to Fifo ?

what components wil the h/w have for synchronizer ?

Can someone help in this doubt ?

Regards,
Ali

 

[Hubble]

clock domain crossings and asynchroneous signals can be treated as the
same.

If asynchrnous , then we can use hand shake >signal ? but how it wil b
in synchrnous system ?

The same. A system with more than one clock domain is inherently
asynchronoues.

Can i use a fifo and give clk A as reference clk to >Fifo ?

Yes. Also DPRAMS are common.

what components wil the h/w have for >synchronizer ?

If you only have to synchronize a single (interrupt) signal, a chain of
two D-Flipflops will do.

Async Input -> DFF1 -> DFF2

DFF1 and DFF2 are clocked by the target clock domain.

what components wil the h/w have for synchronizer ?

If your library contains metastabile hardened flip flops, use one of
these for DFF1. DFF2 should be a standard flip flop.

If you don't have metastabile hardened flip flops, use a normal
D-Flipflop for DFF1. There is a small chance that a metastabile state
will propagate into the design, leaving to an undefined state. With
metastabile hardend ffs, the probability is zero. With two ffs and
modern hardware, the probability of this is once in several (tenth of)
years. Other errors are more likely.

Hubble.

 

jahaya@gmail.com schrieb:

I have a basic doubt in digital design, Suppose if I have a 20mhz clock
domain A and say a 50Mhz another clock domain B,Clock domain B sents an
interupt to domain A which operates of 20Mhz, How should i synchonize
this signal to acknowledge the interupt ?

If asynchrnous , then we can use hand shake signal ? but how it wil b
in synchrnous system ?

Same.

Can i use a fifo and give clk A as reference clk to Fifo ?

In general yes (you need at least a Fifo in your library )

what components wil the h/w have for synchronizer ?

Ask your vendor, as we don't k now what h/w you're using. Typically you
use two FF to cross the clock domains.

Summary:

1. Fifo
2. Shiftregister
3. If your clocks edges are alligned together you could thread the
domain crossing as a normal path with 100Mhz clock frequency (as lowest
common multiplier). But be aware of clock skew between the different
clock domains.
4. You could use the signal with an additional watch-circuit that
rejects the gained results if your clock edges come to close to each
other to ensure stable values (only possible if both clocks are way
slower than the path between both domains demands).

bye Thomas