synchronizer and Reset question?

[javid]

Hello,

I would like to know if a two stage syncronizer is implemented in the
following way:


SYNC_NAS: process (CLK, RST)
begin
if (RST = '1') then
NAS_1 <= '1';
elsif ( rising_edge(CLK) ) then
NAS_1 <= NAS;
end if;
end process;

SYNC_NAS_1: process (CLK, RST)
begin
if (RST = '1') then
NAS_2 <= '1';
elsif ( rising_edge(CLK) ) then
NAS_2 <= NAS_1;
end if;
end process;

As you can see I have included the RST signal (in my case an external
asynchronous Reset signal), is this RST signal needed for the two
stage synchronizer?. I mean, should I write the two stage synchronizer
as before or:


SYNC_NAS: process (CLK)
begin
if ( rising_edge(CLK) ) then
NAS_1 <= NAS;
end if;
end process;

SYNC_NAS_1: process (CLK)
begin
if( rising_edge(CLK) ) then
NAS_2 <= NAS_1;
end if;
end process;
-----------------------------------------------------------------------------

And another question about Reset and State Machine:

In my State Machine I have:

....
STATE_FLOPS: process (CLK, RST)
begin
if (RST='1') then
PRESENT_STATE <= S0;
elsif ( rising_edge(CLK) ) then
EPRESENT_STATE <= NEXT_STATE;
end if;
end process;
....

the RST is coming asynchronously from the outside world. should I use
also for the RST signal the two stage synchronizer in order to avoid
glitches?


Thanks a lot and best regards,

Javi

 

[Mike Treseler]

javodv@yahoo.es (javid) wrote in message news:<c10cd8da.0406240644.748bc803@posting.google.com>...

Hello,

I would like to know if a two stage syncronizer is implemented in the
following way:

Looks ok, but I didn't try it.
I attached a more generalized example below.

As you can see I have included the RST signal (in my case an external
asynchronous Reset signal), is this RST signal needed for the two
stage synchronizer?. I mean, should I write the two stage synchronizer
as before or:

I would leave the reset in unless there is
a real good reason not to.

And another question about Reset and State Machine:

the RST is coming asynchronously from the outside world. should I use
also for the RST signal the two stage synchronizer in order to avoid
glitches?

Yes, if the power-up reset is not already synchronized.

-- Mike Treseler



-------------------------------------------------------------------------------
-- Synchronizer Example Thu Jun 24 11:45:45 2004 Mike Treseler
-- Handles in_len inputs and outputs

-- vsim test_dqdq -do "add wave *; run -all"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dqdq is
generic (in_len : positive := 4;
pipe_len : positive := 2); -- 2 or 3
-- normally 2 levels of synchronization [dq][dq] Watch for reg dups
-- 3 levels covers synthesis register duplication [dq][dq]-.-[dqa]
-- Provides min of two non-duplicated stages \-[dqb]
port (
clk : in std_ulogic;
rst : in std_ulogic;
raw : in std_logic_vector(in_len-1 downto 0); -- unsychronized
cooked : out std_logic_vector(in_len-1 downto 0) -- sychronized
);
end dqdq;

architecture synth of dqdq is

signal A,B,C,D : std_ulogic;
-- Example of internal synchronized signals for another process

begin
synchronize: process (clk, rst) is
-- purpose: put two d flops in line with input vector
subtype vec is std_logic_vector(raw'range);
variable cooked_v : vec;
type shft is array (1 to pipe_len) of vec;
variable pipe_v: shft;
constant clr_pipe : shft := (pipe_v'range => (vec'range => '0'));
procedure sync_this
( i_arg : in std_logic_vector; -- unsynch input vector
p_arg : inout shft; -- pipeline shifter
o_arg : out std_logic_vector) -- synched output vector
is begin
p_arg := i_arg & p_arg(1 to pipe_len-1); -- shift in i_arg vec
o_arg := p_arg(pipe_v'length); -- output vec off the end
end procedure sync_this;

begin
if rst = '1' then
pipe_v := clr_pipe;
cooked <= clr_pipe(1);
elsif rising_edge(clk) then
sync_this(i_arg => raw, p_arg => pipe_v, o_arg => cooked_v);
cooked <= cooked_v; -- output to port if need be
(A,B,C,D) <= cooked_v; -- normally wire to another process
end if;
end process synchronize;
end synth;
-------------------------------------------------------------------------------