Synchronize multiple boards with a pair of lvds

L

LilacSkin

Guest
Hello,

In order to synchronize multiple boards, I want to use a pair of lvds.

All my boards are clocked with the same frequency, and when the
master board receive a "trigger enable", I want it sends signals (with
the pair of lvds) to the other boards in order to synchronize them.

Do you have an idea how to do that with a state machine, I suppose ?

Regards,
Laurent.
 
On Mar 21, 12:03 pm, LilacSkin <lpaul...@iseb.fr> wrote:
Hello,

In order to synchronize multiple boards, I want to use a pair of lvds.

All my boards are clocked with the same frequency,  and when the
master board receive a "trigger enable", I want it sends signals (with
the pair of lvds) to the other boards in order to synchronize them.

Do you have an idea how to do that with a state machine, I suppose ?

Regards,
Laurent.
Is there some reason the obvious approach (below) won't meet some
requirement that you left out of your post?

Sync_To_Other_Boards <= Trigger_Enable;

KJ
 
LilacSkin wrote:

In order to synchronize multiple boards, I want to use a pair of lvds.
All my boards are clocked with the same frequency, and when the
master board receive a "trigger enable", I want it sends signals (with
the pair of lvds) to the other boards in order to synchronize them.
Do you have an idea how to do that with a state machine, I suppose ?
I suppose.
I would also consider buying a core
for one lane of pci express bus.

-- Mike Treseler
 
"LilacSkin" <lpaulo07@iseb.fr> wrote in message
news:ed9fc852-2277-4d92-9e84-401454222d94@z38g2000hsc.googlegroups.com...
Hello,

In order to synchronize multiple boards, I want to use a pair of lvds.

All my boards are clocked with the same frequency, and when the
master board receive a "trigger enable", I want it sends signals (with
the pair of lvds) to the other boards in order to synchronize them.

Do you have an idea how to do that with a state machine, I suppose ?

Regards,
Laurent.
Assuming it meets your data rate requirements I would use a simple biphase
mark code for the inter-board data. This is trivial to generate and decode
if you are willing to operate the link at, say, 1/16 the master clock speed,
and it doesn't require synchronization or preambles like Manchester or
differential Manchester encoding.
 

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