Synchronising Reset APP Note

[Benjamin Todd]

Hi everyone,
Following the discussions about synchronising the Asynch reset of a circuit,
can anyone point me in the direction of an App Note, or a study that shows
the problems of NOT performing the synchronisation of an external Reset?
(Described in "Bulletproofing CPLD design" thread earlier)
Thanks!
Ben

 

Asynchronous & Synchronous Reset
Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson

Rgds
André

 

[Benjamin Todd]

Thanks!
http://www.trilobyte.com/pdf/CummingsSNUG2003Boston_Resets_rev1_2.pdf
for those who are looking too.
Also found a nice article on Xilinx web-site.
Ben
<ALuPin@web.de> wrote in message
news:1123502724.955998.313500@z14g2000cwz.googlegroups.com...
Asynchronous & Synchronous Reset
Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson

Rgds
André