A
Aubrey Jaffer
Guest
This message announces the availability of SIMSYNCH release synch1b7.
New in synch1b7:
* fifo8.scm: Added trivial SimSynch FIFO design example.
* uart.scm (stim:read, stim:write): Added stim sequence.
Added nontrivial SimSynch design example in progress.
* logical.vhd: (Copyright): Added with SLIB-like license.
(Must_Be_Valid): Suppress errors during first 10.ns
of simulation.
* run.scm (translate): Moved translator mapping to usercat.
Added solidify-database call.
* usercat (machxl, verilog, vhdl): Added translator features.
* synch.texi (Infrastructure): Added text about database hygiene.
* simsynch.scm (define-synchronous-system): Don't
solidify-database; screwed multi-block designs.
(create-board): Give error message if db-file locked.
* scm2vhdl.scm (infix-translate-pairwise):
Added to fix multi-argument comparisons;
replaces translate-<> and translate-=.
* models.scm (fifo:clear): array-fill! <- uniform-vector-fill!.
* Makefile (synch_toc.html): Restored.
(synch$(VERSION).info): Added --no-warn.
-=-=-
SIMSYNCH is a simulator for digital electronics at scales from chip to
board.
The design files are comprised of Scheme definitions and expressions.
These design files can be run as a Scheme program at high speed. The
design files can also be translated into formats suitable for logic
compilers (MACHXL, Verilog, and VHDL).
SIMSYNCH simulates blocks of synchronous logic, signals whose states
change simultaneously on a clock signal transition. Each block also
has a reset signal, which forces all signals to the state specified in
the design file. SIMSYNCH can simultaneously simulate multiple blocks
with different clocks and resets. Devices can contain multiple blocks;
Blocks can span multiple devices.
SIMSYNCH is an application of the SCM Scheme implementation.
Documentation is included in the distribution. Documentation is also
online at:
http://swissnet.ai.mit.edu/~jaffer/SIMSYNCH.html
SIMSYNCH source is available from:
http://swissnet.ai.mit.edu/ftpdir/scm/synch1b7.zip
swissnet.ai.mit.edu:/pub/scm/synch1b7.zip (FTP instructions follow)
SCM is the Scheme implementation under which SIMSYNCH runs.
http://swissnet.ai.mit.edu/ftpdir/scm/scm5d8.zip
swissnet.ai.mit.edu:/pub/scm/scm5d8.zip
SLIB is a Scheme library which SCM and SIMSYNCH use:
http://swissnet.ai.mit.edu/ftpdir/scm/slib2d6.zip
swissnet.ai.mit.edu:/pub/scm/slib2d6.zip
Programs for printing and viewing TexInfo documentation (which
SIMSYNCH has) come with GNU Emacs or can be obtained via ftp from:
ftp.gnu.org
ub/gnu/texinfo/texinfo-4.0.tar.gz
-=-=-
ftp swissnet.ai.mit.edu (anonymous)
bin
cd pub/scm
get synch1b7.zip
get slib2d6.zip
get scm5d8.zip
Remember to use binary mode when transferring the files.
Be sure to get and read the GNU General Public License (COPYING).
It is included in synch1b7.zip.
New in synch1b7:
* fifo8.scm: Added trivial SimSynch FIFO design example.
* uart.scm (stim:read, stim:write): Added stim sequence.
Added nontrivial SimSynch design example in progress.
* logical.vhd: (Copyright): Added with SLIB-like license.
(Must_Be_Valid): Suppress errors during first 10.ns
of simulation.
* run.scm (translate): Moved translator mapping to usercat.
Added solidify-database call.
* usercat (machxl, verilog, vhdl): Added translator features.
* synch.texi (Infrastructure): Added text about database hygiene.
* simsynch.scm (define-synchronous-system): Don't
solidify-database; screwed multi-block designs.
(create-board): Give error message if db-file locked.
* scm2vhdl.scm (infix-translate-pairwise):
Added to fix multi-argument comparisons;
replaces translate-<> and translate-=.
* models.scm (fifo:clear): array-fill! <- uniform-vector-fill!.
* Makefile (synch_toc.html): Restored.
(synch$(VERSION).info): Added --no-warn.
-=-=-
SIMSYNCH is a simulator for digital electronics at scales from chip to
board.
The design files are comprised of Scheme definitions and expressions.
These design files can be run as a Scheme program at high speed. The
design files can also be translated into formats suitable for logic
compilers (MACHXL, Verilog, and VHDL).
SIMSYNCH simulates blocks of synchronous logic, signals whose states
change simultaneously on a clock signal transition. Each block also
has a reset signal, which forces all signals to the state specified in
the design file. SIMSYNCH can simultaneously simulate multiple blocks
with different clocks and resets. Devices can contain multiple blocks;
Blocks can span multiple devices.
SIMSYNCH is an application of the SCM Scheme implementation.
Documentation is included in the distribution. Documentation is also
online at:
http://swissnet.ai.mit.edu/~jaffer/SIMSYNCH.html
SIMSYNCH source is available from:
http://swissnet.ai.mit.edu/ftpdir/scm/synch1b7.zip
swissnet.ai.mit.edu:/pub/scm/synch1b7.zip (FTP instructions follow)
SCM is the Scheme implementation under which SIMSYNCH runs.
http://swissnet.ai.mit.edu/ftpdir/scm/scm5d8.zip
swissnet.ai.mit.edu:/pub/scm/scm5d8.zip
SLIB is a Scheme library which SCM and SIMSYNCH use:
http://swissnet.ai.mit.edu/ftpdir/scm/slib2d6.zip
swissnet.ai.mit.edu:/pub/scm/slib2d6.zip
Programs for printing and viewing TexInfo documentation (which
SIMSYNCH has) come with GNU Emacs or can be obtained via ftp from:
ftp.gnu.org
ub/gnu/texinfo/texinfo-4.0.tar.gz-=-=-
ftp swissnet.ai.mit.edu (anonymous)
bin
cd pub/scm
get synch1b7.zip
get slib2d6.zip
get scm5d8.zip
Remember to use binary mode when transferring the files.
Be sure to get and read the GNU General Public License (COPYING).
It is included in synch1b7.zip.