Syn. Warning .

[pradeep]

Hi,

When I synthesised my RAM module in Leonardo spectrum I got the warning as

Warning: Index value 0 to 63 could be out of prefix index constraint 0 to 47.

reg [5:0] ram_slot [0:47] ;
reg [5:0]rd_addr

Always
Begin
:
:
if (read_en)
data_out <= ram_slot [rd_addr] ; ------ WARNING IN THIS LINE
end

How can I overcome this warning?

With regards
Pradeep. G

 

On 2 Mar 2004 03:44:21 -0800, pradeepg@vlsi1.sastra.edu (pradeep)
wrote:

Hi,

When I synthesised my RAM module in Leonardo spectrum I got the warning as

Warning: Index value 0 to 63 could be out of prefix index constraint 0 to 47.

reg [5:0] ram_slot [0:47] ;
reg [5:0]rd_addr

Always
Begin
:
:
if (read_en)
data_out <= ram_slot [rd_addr] ; ------ WARNING IN THIS LINE
end

How can I overcome this warning?

With regards
Pradeep. G

As the tool is complaining, rd_addr can get values up to 63 but you
have only 48 entries in the memory. So ram_slot[rd_addr] can be
invalid for some values of rd_addr. You can remove this warning by
either making ram_slot 64 long or by putting the addressing into a
case on rd_addr and reading ram_slot by constant numbers ie

case(rd_addr)
6'h0: data_out <= ram_slot[0];
....

etc.

 

[John_H]

To avoid the warning either 1) specify the memory as a 64-deep memory

reg [5:0] ram_slot [0:63];

or 2) make the read a bit more complex with 3 individual 16-deep memories

data_out <= rd_addr[5] ? ram_slot2[rd_addr[3:0]]
: rd_addr[4] ? ram_slot1[rd_addr[3:0]]
: ram_slot0[rd_addr[3:0]];

(sorry for any ugly variable-font width formatting)


"pradeep" <pradeepg@vlsi1.sastra.edu> wrote in message
news:962c2d3.0403020344.683c1734@posting.google.com...

Hi,

When I synthesised my RAM module in Leonardo spectrum I got the warning as

Warning: Index value 0 to 63 could be out of prefix index constraint 0 to
47.

reg [5:0] ram_slot [0:47] ;
reg [5:0]rd_addr

Always
Begin
:
:
if (read_en)
data_out <= ram_slot [rd_addr] ; ------ WARNING IN THIS LINE
end

How can I overcome this warning?

With regards
Pradeep. G

 

[pradeep]

Thank u all

To avoid the warning either 1) specify the memory as a 64-deep memory

reg [5:0] ram_slot [0:63];

IN MY DESIGN MEMORY SIZE IS 0 TO 47,
SO IS THERE ANY OPTION TO SPECIFY THE RD_ADDR RANGE AS 6'B000000 TO 6'B101111


Mr. jools

Your indexes should be real numbers already assigned i.e to parameters. This > may fix it.

CAN U PLEASE ELABORATE IT.

THANK U
G.PRADEEP.

 

[John_H]

"pradeep" <pradeepg@vlsi1.sastra.edu> wrote in message
news:962c2d3.0403030321.24c29cd@posting.google.com...

Thank u all

To avoid the warning either 1) specify the memory as a 64-deep memory

reg [5:0] ram_slot [0:63];

IN MY DESIGN MEMORY SIZE IS 0 TO 47,
SO IS THERE ANY OPTION TO SPECIFY THE RD_ADDR RANGE AS 6'B000000 TO
6'B101111

Yikes, it's like you're yelling in here - please limit your use of caps.
Please note that the original problem you had is a WARNING. The warning
will not keep your design from compiling or simulating. You can have your
48 entry memory. If you're in an FPGA, a 48 entry memory will probably be
implemented with 64 entries. Some ASIC memories may also give you binary
multiples of entries rather than provide a memory generator that handles
non-binary multiples.

If you want your code to be without warnings, you'll have to make some
compromises. It's *possible* that the vendor's toolset that produced that
warning could have directives to define odd-sized memories without the
warning, but it's doubtful.

Mr. jools

Your indexes should be real numbers already assigned i.e to parameters.
This > may fix it.

CAN U PLEASE ELABORATE IT.

THANK U
G.PRADEEP.

 

[Andy Peters]

pradeepg@vlsi1.sastra.edu (pradeep) wrote in message news:<962c2d3.0403030321.24c29cd@posting.google.com>...

Thank u all

To avoid the warning either 1) specify the memory as a 64-deep memory

reg [5:0] ram_slot [0:63];

IN MY DESIGN MEMORY SIZE IS 0 TO 47,
SO IS THERE ANY OPTION TO SPECIFY THE RD_ADDR RANGE AS 6'B000000 TO 6'B101111

No, this ain't VHDL.

-a